Recommended Decoupling Capacitor Quantities for Artix UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ XC Devices

XCAU7P-FCVA289

1

1

1

2

2

1

1

1

1

1

1

1

1

XCAU7P-UBVA292

1

1

1

2

2

1

1

1

1

1

1

1

1

XCAU7P-SBVC484

1

1

1

1

0

1

1

1

1

0

1

1

0

XCAU10P-UBVA368

1

1

1

3

3

1

1

1

2

2

1

1

1

XCAU10P-SBVB484

1

1

1

1

0

1

1

1

1

0

1

1

0

XCAU10P-FFVB676

1

1

1

1

0

1

1

1

1

0

1

1

0

XCAU15P-UBVA368

1

1

2

5

5

1

1

1

2

2

1

1

1

XCAU15P-SBVB484

1

1

1

1

0

1

1

1

1

0

1

1

0

XCAU15P-FFVB676

1

1

1

1

0

1

1

1

1

0

1

1

0

XCAU20P-FFVB676

1

1

1

1

0

1

1

1

1

0

1

1

0

XCAU20P-SFVB784

1

1

2

4

0

1

1

1

1

0

1

1

0

XCAU25P-FFVB676

1

1

1

2

0

1

1

1

2

0

1

1

0

XCAU25P-SFVB784

1

1

1

2

0

1

1

1

2

0

1

1

0

Notes:

1.Connect V_CCINT and V_{CCINT_IO} together on the PCB for -3, -2, and -1 speed grades. The capacitors listed are the total number of capacitors for the combined rail.

2.Connect V_CCBRAM and V_{CCINT_IO} together on the PCB for -2L and -1L speed grades. The capacitors listed are the total number of capacitors for the combined rail.

3.V_CCAUX and V_{CCAUX_IO} must share the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

4.The 47 µF capacitor can be combined at one per every four shared HDIO/HPIO banks.

XCKU3P-SFVB784

1

4

1

1

1

1

1

1

1

1

XCKU3P-FFVA676

1

4

1

1

1

1

1

1

1

1

XCKU3P-FFVB676

1

4

1

1

1

1

1

1

1

1

XCKU3P-FFVD900

1

4

1

1

1

1

1

1

1

1

XCKU5P-SFVB784

1

5

1

1

1

1

1

1

1

1

XCKU5P-FFVA676

1

5

1

1

1

1

1

1

1

1

XCKU5P-FFVB676

1

5

1

1

1

1

1

1

1

1

XCKU5P-FFVD900

1

5

1

1

1

1

1

1

1

1

XCKU9P-FFVE900

1

5

1

1

1

1

1

1

1

1

XCKU11P-FFVD900

1

5

1

1

1

1

1

1

1

1

XCKU11P-FFVA1156

1

5

1

1

1

1

1

1

1

1

XCKU11P-FFVE1517

1

5

1

1

1

1

1

1

1

1

XCKU13P-FFVE900

1

5

1

1

1

1

1

1

1

1

XCKU15P-FFVA1156

1

5

1

1

1

1

1

1

1

1

XCKU15P-FFVE1517

1

5

1

1

1

1

1

1

1

1

XCKU15P-FFVA1760

1

5

1

1

1

1

1

1

1

1

XCKU15P-FFVE1760

1

5

1

1

1

1

1

1

1

1

XCKU19P-FFVJ1760

1

5

1

1

1

1

2

2

1

1

XCKU19P-FFVB2104

1

5

1

1

1

1

2

2

1

1

Notes:

1.Connect V_CCINT and V_{CCINT_IO} together on the PCB for -3, -2, and -1 speed grades. The capacitors listed are the total number of capacitors for the combined rail.

2.Connect V_CCBRAM and V_{CCINT_IO} together on the PCB for -2L and -1L speed grades. The capacitors listed are the total number of capacitors for the combined rail.

3.V_CCAUX and V_{CCAUX_IO} must share the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

4.The 47 µF capacitor can be combined at one per every four shared HDIO/HPIO banks.

XCVU3P-FFVC1517

1

5

1

1

1

1

1

1

1

1

XCVU5P-FLVA2104

2

6

1

1

1

1

2

2

1

1

XCVU5P-FLVB2104

2

6

1

1

1

1

2

2

1

1

XCVU5P-FLVC2104

2

6

1

1

1

1

2

2

1

1

XCVU7P-FLVA2104

2

7

2

2

1

1

2

2

1

1

XCVU7P-FLVB2104

2

7

2

2

1

1

2

2

1

1

XCVU7P-FLVC2104

2

7

2

2

1

1

2

2

1

1

XCVU9P-FLGA2104

3

8

3

4

1

2

2

2

1

1

XCVU9P-FLGB2104

3

8

3

4

1

2

2

2

1

1

XCVU9P-FLGC2104

3

8

3

4

1

2

2

2

1

1

XCVU9P-FSGD2104

3

8

3

4

1

2

2

2

1

1

XCVU9P-FLGA2577

3

8

3

4

1

2

2

2

1

1

XCVU11P-FLGF1924

4

9

4

8

1

2

1

2

1

1

XCVU11P-FLGB2104

4

9

4

8

1

2

1

2

1

1

XCVU11P-FLGC2104

XQVU11P-FLRC2104

4

9

4

8

1

2

1

2

1

1

XCVU11P-FSGD2104

4

9

4

8

1

2

1

2

1

1

XCVU11P-FLGA2577

4

9

4

8

1

2

1

2

1

1

XCVU13P-FHGA2104

5

11

6

16

1

2

2

2

1

1

XCVU13P-FHGB2104

5

11

6

16

1

2

2

2

1

1

XCVU13P-FHGC2104

5

11

6

16

1

2

2

2

1

1

XCVU13P-FIGD2104

5

11

6

16

1

2

2

2

1

1

XCVU13P-FLGA2577

5

11

6

16

1

2

2

2

1

1

XCVU13P-FSGA2577

5

11

6

16

1

2

2

2

1

1

XCVU19P-FSVA3824⁽⁵⁾⁽⁷⁾

5

11

26

14

2

3

3

5

1

1

XCVU19P-FSVA3824 (thicker boards)⁽⁶⁾⁽⁷⁾

5

11

40

40

4

4

6

6

1

2

XCVU19P-FSVB3824⁽⁵⁾⁽⁷⁾

5

11

26

14

2

3

3

5

1

1

XCVU19P-FSVB3824 (thicker boards)⁽⁶⁾⁽⁷⁾

5

11

40

40

4

4

6

6

1

2

XCVU23P-VSVA1365

2

6

1

1

1

1

2

2

1

1

XCVU23P-FSVJ1760

2

6

1

1

1

1

2

2

1

1

Notes:

1.Connect V_CCINT and V_{CCINT_IO} together for -3, -2, and -1 speed grades. The capacitors listed are the total number of capacitors for the combined rail.

2.Connect V_CCBRAM and V_{CCINT_IO} together for -2L and -1L speed grades. The capacitors listed are the total number of capacitors for the combined rail.

3.V_CCAUX and V_{CCAUX_IO} must share the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

4.The 47 µF capacitor can be combined at one per every four HPIO banks.

5.The XCVU19P devices have land-side capacitors (LSCs) on the bottom side of the packages, which leads to fewer 10 µF capacitors required on the PCB compared to other similar sized devices.

6.This is for boards approximately ³ 200 mil thickness.

7.The XCVU19P devices are recommended to be edge bonded. Refer to the Thermal Specifications chapter of UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) [Ref 9] for edge bonding guidelines.

XCVU27P-FIGD2104

3

9

4

8

1

2

1

2

1

1

XCVU27P-FSGA2577

3

9

4

8

1

2

1

2

1

1

XCVU29P-FIGD2104

4

10

6

15

1

2

2

2

1

1

XCVU29P-FSGA2577

4

10

6

15

1

2

2

2

1

1

Notes:

1.For non -2LE devices, combine V_CCINT, V_CCBRAM, V_{CCINT_IO}, and V_{CCINT_GT} to the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

2.For -2LE devices, V_CCINT is standalone. Combine V_CCBRAM, V_{CCINT_IO}, and V_{CCINT_GT} to the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

3.V_CCAUX and V_{CCAUX_IO} must share the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

4.The 47 µF capacitor can be combined at one per every four shared HPIO banks.

XCVU31P-FSVH1924

1

5

1

1

1

2

1

1

1

1

XCVU33P-FSVH2104

1

5

1

1

1

2

1

1

1

1

XCVU35P-FSVH2104

2

7

2

2

1

2

1

1

1

1

XCVU35P-FSVH2892

2

7

2

2

1

2

1

1

1

1

XCVU37P-FSVH2892

3

9

4

8

1

2

2

2

1

1

XCVU45P-FSVH2104

2

7

2

2

1

2

1

1

1

1

XCVU45P-FSVH2892

2

7

2

2

1

2

1

1

1

1

XCVU47P-FSVH2892

3

9

4

8

1

2

2

2

1

1

XCVU57P-FSVK2892

3

9

4

8

1

2

2

2

1

1

Notes:

1.V_CCINT can be standalone or combined with V_CCBRAM and V_{CCINT_IO} on the same plane. The capacitors listed are the total number of capacitors for the combined rail.

2.V_CCAUX and V_{CCAUX_IO} must share the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

3.The 47 µF capacitor can be combined at one per every four shared HPIO banks.

VU31P, VU33P,

VU35P, VU37P,

VU45P, VU47P

VU57P

1

1

2

1

1

1

1

1

Notes:

1.These recommendations are per stack.

2.The step load assumption for V_{CC_HBM} is approximately 1A per stack, and approximately 2A per stack for V_{CC_IO_HBM}.