Recommended Decoupling Capacitor Quantities for Kintex UltraScale and Virtex UltraScale Commercial Grade (XC) Devices

UltraScale Architecture PCB Design User Guide (UG583)
Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

Table: Devices Decoupling Capacitor Recommendations for Kintex UltraScale XC Devices and Table: Devices Decoupling Capacitor Recommendations for Virtex UltraScale XC Devices show the recommended decoupling capacitor quantities for Kintex UltraScale and Virtex UltraScale commercial grade (XC) devices.

Table A-1:      Devices Decoupling Capacitor Recommendations for Kintex UltraScale XC Devices

 

VCCINT/VCCINT_IO(1)

VCCBRAM

VCCAUX/VCCAUX_IO(2)

HRIO/HPIO(3) (per bank)

330 µF

100 µF

47 µF

10 µF

47 µF

10 µF

47 µF

10 µF

47 µF

10 µF

XCKU025-FFVA1156

1

4

1

1

1

1

1

1

1

1

XCKU035-FBVA676

1

5

1

1

1

1

1

1

1

1

XCKU035-SFVA784

1

5

1

1

1

1

1

1

1

1

XCKU035-FBVA900

1

5

1

1

1

1

1

1

1

1

XCKU035-FFVA1156

1

5

1

1

1

1

1

1

1

1

XCKU040-FBVA676

1

5

1

1

1

1

1

1

1

1

XCKU040-SFVA784

1

5

1

1

1

1

1

1

1

1

XCKU040-FBVA900

1

5

1

1

1

1

1

1

1

1

XCKU040-FFVA1156

1

5

1

1

1

1

1

1

1

1

XCKU060-FFVA1156

1

5

1

1

1

1

1

1

1

1

XCKU060-FFVA1517

1

5

1

1

1

1

1

1

1

1

XCKU085-FLVA1517

2

6

1

1

1

1

1

1

1

1

XCKU085-FLVB1760

2

6

1

1

1

1

1

1

1

1

XCKU085-FLVF1924

2

6

1

1

1

1

1

2

1

1

XCKU095-FFVA1156

1

5

1

1

1

1

1

1

1

1

XCKU095-FFVC1517

1

5

1

1

1

1

1

1

1

1

XCKU095-FFVB1760

1

5

1

1

1

1

1

1

1

1

XCKU095-FFVB2104

1

5

1

1

1

1

1

2

1

1

XCKU115-FLVA1517

2

7

2

2

1

1

1

1

1

1

XCKU115-FLVD1517

2

7

2

2

1

1

1

1

1

1

XCKU115-FLVB1760

2

7

2

2

1

1

1

1

1

1

XCKU115-FLVD1924

2

7

2

2

1

1

1

1

1

1

XCKU115-FLVF1924

2

7

2

2

1

1

1

2

1

1

XCKU115-FLVA2104

2

7

2

2

1

1

1

2

1

1

XCKU115-FLVB2104

2

7

2

2

1

1

1

2

1

1

Notes:

1.Assumes combined VCCINT/VCCINT_IO plane or combined VCCINT/VCCINT_IO/VCCBRAM plane. The capacitors listed are the total number of capacitors for the combined rail.

2.VCCAUX and VCCAUX_IO must share the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

3.The 47 µF capacitor can be combined at one per every four shared HRIO/HPIO banks.
Table A-2:      Devices Decoupling Capacitor Recommendations for Virtex UltraScale XC Devices

 

VCCINT/VCCINT_IO(1)

VCCBRAM

VCCAUX/VCCAUX_IO(2)

HRIO/HPIO(3) (per bank)

330 µF

100 µF

47 µF

10 µF

47 µF

10 µF

47 µF

10 µF

47 µF

10 µF

XCVU065-FFVC1517

1

5

1

1

1

1

1

1

1

1

XCVU080-FFVC1517

1

5

1

1

1

1

1

1

1

1

XCVU080-FFVD1517

1

5

1

1

1

1

1

1

1

1

XCVU080-FFVB1760

1

5

1

1

1

1

1

1

1

1

XCVU080-FFVA2104

1

5

1

1

1

1

1

2

1

1

XCVU080-FFVB2104

1

5

1

1

1

1

1

2

1

1

XCVU095-FFVC1517

1

5

1

1

1

1

1

1

1

1

XCVU095-FFVD1517

1

5

1

1

1

1

1

1

1

1

XCVU095-FFVB1760

1

5

1

1

1

1

1

1

1

1

XCVU095-FFVA2104

1

5

1

1

1

1

1

2

1

1

XCVU095-FFVB2104

1

5

1

1

1

1

1

2

1

1

XCVU095-FFVC2104

1

5

1

1

1

1

1

1

1

1

XCVU125-FLVD1517

2

6

1

1

1

1

1

1

1

1

XCVU125-FLVB1760

2

6

1

1

1

1

1

1

1

1

XCVU125-FLVA2104

2

6

1

1

1

1

1

2

1

1

XCVU125-FLVB2104

2

6

1

1

1

1

1

2

1

1

XCVU125-FLVC2104

2

6

1

1

1

1

1

2

1

1

XCVU160-FLGB2104

2

7

2

2

1

1

1

2

1

1

XCVU160-FLGC2104

2

7

2

2

1

1

1

2

1

1

XCVU190-FLGB2104

3

7

3

1

1

1

1

2

1

1

XCVU190-FLGC2104

3

7

3

1

1

1

1

2

1

1

XCVU190-FLGA2577

3

7

3

1

1

1

1

2

1

1

XCVU440-FLGB2377

5

11

7

17

1

2

2

4

1

1

XCVU440-FLGA2892

5

11

7

17

1

2

2

4

1

1

Notes:

1.Assumes combined VCCINT/VCCINT_IO plane or combined VCCINT/VCCINT_IO/VCCBRAM plane. The capacitors listed are the total number of capacitors for the combined rail.

2.VCCAUX and VCCAUX_IO must share the same plane on the PCB. The capacitors listed are the total number of capacitors for the combined rail.

3.The 47 µF capacitor can be combined at one per every four shared HRIO/HPIO banks.