FPGA Mounting Inductance

The PCB solder lands and vias that connect the FPGA power pins (V_CC and GND) contribute an amount of parasitic inductance to the overall power circuit. For existing PCB technology, the solder land geometry and the dogbone geometry are mostly fixed, and parasitic inductance of these geometries does not vary. Via parasitic inductance is a function of the via length and the proximity of the opposing current paths to one another.

The relevant via length is the portion of the via that carries transient current between the FPGA solder land and the associated V_CC or GND plane. Any remaining via (between the power plane and the PCB backside) does not affect the parasitic inductance of the via (the shorter the via between the solder lands and the power plane, the smaller the parasitic inductance). Parasitic via inductance in the FPGA mounting is reduced by keeping the relevant V_CC and GND planes as close to the FPGA as possible (close to the top of the PCB stackup).

Device pinout arrangement determines the proximity of opposing current paths to one another. Inductance is associated with any two opposing currents (for example, current flowing in a V_CC and GND via pair). A high degree of mutual inductive coupling between the two opposing paths reduces the loop’s total inductance. Therefore, when given a choice, V_CC and GND vias should be as close together as possible.

The via field under an FPGA has many V_CC and GND vias, and the total inductance is a function of the proximity of one via to another:

•For core V_CC supplies (V_CCINT and V_CCAUX ), opposing current is between the V_CC and GND pins.

•For I/O V_CC supplies (V_CCO ), opposing current is between any I/O and its return current path, whether carried by a V_CCO or GND pin.

To reduce parasitic inductance:

•Core V_CC pins such as V_CCINT and V_CCAUX are placed in a checkerboard arrangement in the pinout.

•V_CCO and GND pins are distributed among the I/O pins.

Every I/O pin in the Kintex UltraScale and Virtex UltraScale FPGA pinouts is adjacent to a return-current pin.

FPGA pinout arrangement determines the PCB via arrangement. The PCB designer cannot control the proximity of opposing current paths but has control over the trade-offs between the capacitor’s mounting inductance and FPGA’s mounting inductance:

•Both mounting inductances are reduced by placing power planes close to the PCB stackup’s top half and placing the capacitors on the top surface (reducing the capacitor’s via length).

•If power planes are placed in the PCB stackup’s bottom half, the capacitors are recommended to be mounted on the PCB backside. In this case, FPGA mounting vias are already long, and making the capacitor vias long (by coming down from the top surface) is a bad practice. A better practice is to take advantage of the short distance between the underside of the PCB and the power plane of interest, mounting capacitors on the underside.