Recommended Decoupling Capacitor Quantities for UltraScale+ Automotive (XA) Devices

UltraScale Architecture PCB Design User Guide (UG583)
Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

UltraScale+ automotive devices (XA) require different capacitor types and quantities versus commercial (XC) devices due to higher temperature requirements. These higher requirements result in capacitor case sizes that are bigger than for lower temperature ranges. As such, bigger case sizes lead to higher inductances, requiring more capacitors.   Also, higher temperature capacitors tend to have less capacitance per a given case size which also results in higher capacitor quantities required.

Table: Programmable Logic Rail Decoupling Guidelines for Artix UltraScale+ XA Devices through Table: VCCINT_VCU Decoupling Guidelines for Zynq UltraScale+ XA Devices list the decoupling requirements for Artix UltraScale+ and Zynq UltraScale+ automotive devices (XA).

Table B-1:      Programmable Logic Rail Decoupling Guidelines for Artix UltraScale+ XA Devices

 

VCCINTVCCBRAM/VCCINT_IO(1)

VCCBRAM/VCCINT_IO(1)

VCCAUX/VCCAUX_IO(2)

HDIO/HPIO(3)

100 µF

22 µF

10 µF

2.2 µF

1.0 µF

22 µF

10 µF

22 µF

10 µF

22 µF

10 µF

XAAU7P-SBVC484

1

1

1

1

1

1

1

2

1

1

1

XAAU10P-SVBV484

1

2

3

4

1

1

1

3

1

1

1

XAAU10P-FFVB676

2

2

1

1

1

1

1

3

1

1

1

XAAU15P-SVBV484

1

3

3

5

3

1

1

3

1

1

1

XAAU15P-FFVB676

2

3

1

1

1

1

1

3

1

1

1

Notes:

1.Connect VCCINT standalone, and VCCBRAM/VCCINT_IO together on the PCB for L speed grades.

2.VCCAUX and VCCAUX_IO must share the same plane on the PCB.

3.The 22 µF capacitor can be combined at one per every four shared HDIO/HPIO banks.
Table B-2:      Programmable Logic Rail Decoupling Guidelines for Zynq UltraScale+ XA Devices

 

VCCINTVCCBRAM/VCCINT_IO(1)

VCCBRAM/VCCINT_IO(1)

VCCAUX/VCCAUX_IO(2)

HDIO/HPIO(3)

100 µF

22 µF

10 µF

2.2 µF

1.0 µF

22 µF

10 µF

22 µF

10 µF

22 µF

10 µF

XAZU1EG-SBVA484

1

1

2

3

0

1

1

3

1

1

1

XAZU1EG-SFVA625

1

1

2

3

0

1

1

3

1

1

1

XAZU1EG-SFVC784

1

1

2

3

0

1

1

3

1

1

1

XAZU2EG-SBVA484

1

2

1

4

0

1

1

3

1

1

1

XAZU2EG-SFVA625

1

2

1

4

0

1

1

3

1

1

1

XAZU2EG-SFVC784

1

2

1

4

0

1

1

3

1

1

1

XAZU3EG-SBVA484

1

2

3

4

2

1

1

3

1

1

1

XAZU3EG-SFVA625

1

2

3

4

2

1

1

3

1

1

1

XAZU3EG-SFVC784

1

2

3

4

2

1

1

3

1

1

1

XAZU3TEG-SFVD784

2

3

4

5

5

1

1

3

1

1

1

XAZU4EV-SFVC784

2

3

4

5

5

1

1

3

1

1

1

XAZU5EV-SFVC784

2

5

5

6

8

1

1

3

1

1

1

XAZU7EG-FBVB900

4

8

6

8

3

1

1

3

1

1

1

XAZU7EV-FBVB900

4

8

6

8

3

1

1

3

1

1

1

XAZU11EG-FFVF1517

6

12

11

13

7

1

1

4

1

1

1

Notes:

1.Connect VCCINT standalone, and VCCBRAM/VCCINT_IO together on the PCB for L speed grades.

2.VCCAUX and VCCAUX_IO must share the same plane on the PCB.

3.The 22 µF capacitor can be combined at one per every four shared HDIO/HPIO banks.
Table B-3:      PS Decoupling Guidelines for Zynq UltraScale+ XA Devices

VCC_PSINTFP

VCC_PSINTLP

VCC_PSAUX

VCC_PSPLL

VCC_PSINTFP_DDR

VCCO_PSIOx (Each)(1)

VCC_PSBATT

VCCO_PSDDR

22 µF

10 µF

22 µF

10 µF

10 µF

2.2 µF

22 µF

10 µF

22 µF

10 µF

22 µF

10 µF

22 µF

2.2 µF

22 µF

2.2 µF

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Notes:

1.Can combine 22 µF at one per every four shared VCCO_PSIO banks.

2.For PS_MGTRAVCC and PS_MGTRAVTT, use one 22 µF each.
Table B-4:      VCCINT_VCU Decoupling Guidelines for Zynq UltraScale+ XA Devices

 

VCCINT_VCU

100 µF

22 µF

10 µF

2.2 µF

1.0 µF

XAZU4EV-SFVC784

1

1

1

2

3

XAZU5EV-SFVC784

1

1

1

2

3

XAZU5EV-FBVB900

1

1

1

2

3

XAZU7EV-FBVB900

1

1

1

2

3
Table B-5:      Recommended PCB Capacitor Specifications and Placement Guidelines for XA Devices

Nominal Value (µF)

Case Size

Temp/Change (%)

Manufacturer

Manufacturer Part Number

Ideal Placement to MPSoC(1)

100

1210

X7S

Murata

GRT32EC70J107ME13

1–1.5”

22

0805

X7S

Murata

GRT21BD70J226ME13

0–1”

10

0603

X7T

Murata

GRT188D70J106ME13

0–1”

2.2

0402

X7S

Murata

GRT155C70J225KE13

0–1”

1.0

0201

X7T

Murata

GRT033D70J105ME13

Under BGA

Notes:

1.Ideal placement is to minimize distance between capacitor and MPSoC.

2.AMD recommends placing the 0201 capacitors directly under the MPSoC footprint on the oppose site of the board. This minimizes spreading inductance and results in maximum efficiency.