Example of Tuning Design Parameters to Meet Impedance Targets

Table: Example of Tuning PCB Parameters to Meet Impedance Target shows a target of 36W for stripline impedance in the main L1 PCB area. The trace width (W) is specified as 7.0 mils along with 8.0 mil spacing (S). The reference PCB stackup in Table: Reference Stackup defines the layer composition and dielectric material that will result in reaching 36W. This consists of a 4.0 dielectric constant (D_K), and 9.6 mil layer height (H) (4.5 + 0.6 + 4.5). Table: Example of Tuning PCB Parameters to Meet Impedance Target shows tuning of the trace width (W) and height (H) required to meet the impedance target. The spacing (S) shows how it should change to continue to meet performance requirements, though the spacing is not a factor in the line impedance. When increasing D_K, the signal loss also increases per Table: Relationship of DK to Impedance, Propagation Delay. and Signal Loss.