RLDRAM 3 Memory CK_P/N Fly-by Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This Figure shows the clock differential fly-by routing for RLDRAM 3 memory.

Figure 2-65: Clock Differential Fly-by Routing for RLDRAM 3 Memory
X-Ref Target - Figure 2-65

Table: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Clock Signals shows the RLDRAM 3 memory fly-by impedance, length, and spacing guidelines for clock signals.

Table 2-76: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Clock Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DRAM Breakout)	L3	L4 (To R_TT)	Units
Trace type	Stripline	Stripline	Stripline	Stripline	Stripline	–
Clock differential impedance Z_DIFF	86±10%	76±10%	86±10%	90±10%	76±10%	W
Trace width/space/width	4.0/4.0/4.0	6.0/6.0/6.0	4.0/4.0/4.0	4.0/5.0/4.0	6.0/6.0/6.0	mil
Trace length	0.0~0.8/1.2⁽¹⁾	0.0~3.0	0.0~0.25	0.35~1.05	0~1.0	inches
Spacing in address, command, and control signals (minimum)	8.0	20	8.0	20	20	mil
Spacing to other group signals (minimum)	8.0	30	30	30	30	mil
Maximum PCB via count per signal	4					–
Notes: 1.See item 2 in General Memory Routing Guidelines.