•PCB and package skew between ALE/CE/CLE and CLK should be within ±50 ps.
•To operate in mode 0 to mode 4, PCB and package skew between CLK and DQS should be within ±50 ps.
•To operate in mode 5 at 100 MHz, PCB and package skew between CLK and DQS should be a minimum of 400 ps + 50 ps. CLK should be skewed with respect to DQS by 400 ps.
•PCB and package skew between DQ and DQS should be within ±25 ps.
•Place 4.7 kW pull-up resistors on CE and RB near the NAND device.
•For devices without a DQS pin, the MPSoC MIO pin can be left unconnected or used for another purpose.