Overview

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This section focuses on the selection of the reference clock source or oscillator. An oscillator is characterized by:

•Frequency range

•Output voltage swing

•Jitter (deterministic, random, peak-to-peak)

•Rise and fall times

•Supply voltage and current

•Noise specification

•Duty cycle and duty-cycle tolerance

•Frequency stability

These characteristics are selection criteria when choosing an oscillator for PS-GTR transceiver design. This Figure illustrates the convention for the single-ended clock input voltage swing, peak-to-peak, as used in the PS-GTR transceiver portion of the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22]. This figure is provided to show the contrast to the differential clock input voltage swing calculation shown in This Figure.

Figure 4-2: Single-Ended Clock Input Voltage Swing, Peak-to-Peak
X-Ref Target - Figure 4-2

Figure 4-3: Differential Clock Input Voltage Swing, Peak-to-Peak
X-Ref Target - Figure 4-3

This Figure shows the rise and fall time convention of the reference clock.

Figure 4-4: Rise and Fall Times
X-Ref Target - Figure 4-4

This Figure illustrates the internal details of the MGTREFCLK input buffer. The dedicated differential reference clock input pin pair MGTREFCLKP/MGTREFCLKN is internally terminated with a 100W differential impedance. The common mode voltage of this differential reference clock input pair is ground or nominal 0.0V. See the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) for exact specifications.

Figure 4-5: MGTREFCLK Input Buffer Details
X-Ref Target - Figure 4-5