DDR3 SDRAM Address, Command, and Control Fly-by Termination

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

With high-speed signaling in DDR3 SDRAM, fly-by topology is used for address, command, and control signals to achieve the best signal integrity. Each address, command, and control signal by itself is routed continuously in the same layer from the respective UltraScale device pin to far end termination, except in breakout areas. In other words, each individual address, command, or control signal routing is not broken into routings on multiple layers. This Figure shows the address fly-by termination for DDR3 SDRAM.

Figure 2-28:      Address Fly-by Termination for DDR3 SDRAM

X-Ref Target - Figure 2-28

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