This Figure shows the data signals point-to-point for LPDDR3 SDRAM. For DQ/DM/DQS signals, ODT is available on both the FPGA and SDRAM side.
Table: LPDDR3 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals shows the LPDDR3 SDRAM impedance, length, and spacing guidelines for data signals for both x32 and x64 systems.
Parameter |
L0 |
L1 |
L2 |
Units |
---|---|---|---|---|
Trace type |
Stripline |
Stripline |
Stripline |
- |
DQ single-ended impedance Z0 |
50±10% |
39±10% |
52±10% |
W |
DQS differential impedance Zdiff |
86±10% |
76±10% |
88±10% |
W |
Trace width (nominal) |
4.0 |
6.0 |
3.5 |
mil |
Differential trace width/space/width |
4.0/4.0/4.0 |
6.0/6.0/6.0 |
3.5/3.25/3.5 |
mil |
Trace length (nominal) |
0.0~0.55 |
1.0~4.0 |
0.0~0.3 |
inch |
Spacing in byte (minimum) |
4.0 |
8.0 |
4.0 |
mil |
Spacing byte to byte (minimum) |
4.0 |
20 |
4.0 |
mil |
DQ to DQS spacing (minimum) |
4.0 |
20 |
8.0 |
mil |
Spacing to other group signals (minimum) |
8.0 |
30 |
8.0 |
mil |
Maximum PCB via count |
2 |
mil |
||
Notes: 1.See item 2 in General Memory Routing Guidelines. |