syn.directive.bind_op - 2023.1 English

Description

Vitis HLS implements the different operations in the code using specific hardware resources (or implementations). The tool automatically determines the resource to use, or you can define syn.op can be defined to generally specify the implementation as explained in Operator Configuration.

The syn.directive.bind_op command indicates that for the specified variable an operation (for example mul, add, or sub) should be mapped to a specific implementation (impl) in the RTL. For example, to indicate that a specific multiplier operation (mul) is implemented in the device fabric rather than a DSP, you can use the syn.directive.bind_op command.

You can also specify the latency with syn.directive.bind_op using the latency option as described below.

Syntax

syn.directive.bind_op=[OPTIONS] <location> <variable>

• <location> is the location (in the format function[/label]) which contains the variable.
• <variable> is the variable to be assigned. The variable in this case is one that is assigned the result of the operation that is the target of this directive.

Options

op=<value>

Defines the operation to bind to a specific implementation resource. Supported functional operations include: mul, add, sub

Supported floating point operations include: fadd, fsub, fdiv, fexp, flog, fmul, frsqrt, frecip, fsqrt, dadd, dsub, ddiv, dexp, dlog, dmul, drsqrt, drecip, dsqrt, hadd, hsub, hdiv, hmul, and hsqrt

Tip: Floating-point operations include single precision (f), double-precision (d), and half-precision (h).

impl=<value>

Defines the implementation to use for the specified operation.

Supported implementations for functional operations include fabric and dsp.

Supported implementations for floating point operations include: fabric, meddsp, fulldsp, maxdsp, and primitivedsp.

Note: primitivedsp is only available on Versal devices.

latency=<int>

Defines the default latency for the implementation of the operation. The valid latency varies according to the specified op and impl. The default is -1, which lets Vitis HLS choose the latency.

The tables below reflect the supported combinations of operation, implementation, and latency.

Examples

In the following example, a two-stage pipelined multiplier using fabric logic is specified to implement the multiplication for variable c of the function foo.

int foo (int a, int b) {
int c, d;
c = a*b;
d = a*c;
return d;
}

syn.directive.bind_op=op=mul impl=fabric latency=2 foo c

See Also

• syn.directive.bind_storage