Make sure the HLS component is active in the Flow Navigator, or select Component to make it the active component in the tool. When the HLS component is the active component, the Flow Navigator enables running C Synthesis, C Simulation, C/RTL Co-simulation, and Implementation to build and analyze the HLS component. Select Run beneath the IMPLEMENTATION heading in the Flow Navigator.
The Vitis HLS tool is limited in terms of the estimations it can provide about the RTL design that it generates. It can project resource utilization and timing of the end result, but these are just projections. To get a better view of the RTL design, you can actually run Vivado synthesis and place and route on the generated RTL design, and review actual results of timing and resource utilization. Select the Run Implementation command from the Flow Navigator to open the dialog box as shown below.
Specify the strategy to employ in the implementation run. This is only for use during the implementation run for resource utilization and timing estimates, and does not affect the generated Vivado IP or Vitis kernels.
Configure the Tool
You can configure the simulator prior to running simulation using the C/RTL Co-Simulation section of the Config Editor, as shown below.
The configuration commands for Implementation include:
- Flow
- Specify to run only synthesis or both synthesis and
implementation. Synthesis alone will run faster than both synthesis and
implementation, but will lack some of details of the implementation run. The
default is
impl. - RTL
- Specifies the language to use when running Vivado out-of-context flow.
- Clock Period
- Specify the clock period to use during synthesis or implementation. When not specified, the default clock specified when the HLS component is created is used.
- Implementation Strategy
- Specify the strategy to employ in the implementation run. This is only for use during the implementation run for resource utilization and timing estimates, and does not affect the generated Vivado IP or Vitis kernels.
- Max Timing Paths
- Specify the number of timing paths to extract from the Timing Summary report. The specified number of worst case paths are returned.
- Optimization Level
- This is a general feature to manage the optimizations performed by the Vivado tool. The higher the setting, the more optimizations are employed, and the longer the runtime as a result.
- Pblock
- Specifies a Pblock range or value to use during placement and routing to limit the area available for the design.
- Run Physical Optimizations
- Specify the physical optimization to run. Choices include:
none,place,route, andall - Report Level
- Defines the report-level generated during synthesis or implementation. The report can include the utilization and timing summary, timing path details, or a failfast report, which is the default.
- Synth Design Arguments
- Specify options for the
synth_designcommand. - Synthesis Strategy
- Specify the strategy to employ in the Vivado synthesis run.
Run Implementation
With the Implementation setup defined in the config file you are
ready to select Run from the
Flow Navigator. You
can track the progress of the implementation run in the Output window. The transcript for the run
will have the top function name as <component-name>::implementation as shown below.
The implementation run in the Vitis IDE uses the vitis-run --mode hls
--impl command as described in vitis-run Command. After the simulation is complete you should see the
Implementation finished
successfully message at the end of the transcript. You will
also see the Reports
folder under the Run
command populated with the following reports:
- Summary: Reports the command line used and the time stamp on the results
- RTL Synthesis: Reports the results of synthesis including resource use and timing
- Place and Route: As described in Implementation Report