HLS: General Options - 2023.1 English

Vitis Unified IDE and Common Command-Line Reference Manual (UG1553)
Document ID
UG1553
Release Date
2023-07-17
Version
2023.1 English
board

Specify a Vivado board name for the HLS component to be built for. The selection of board determines the target part on the board.

Tip: This option is mutually exclusive with --part which is described in v++ General Compilation Options.
clock
Specify the clock period in ns or MHz (ns is default). If no period is specified a default period of 10 ns is used. 
clock=8
clock_uncertainty
Specify how much of the clock period is used as a margin by HLS. The margin of uncertainty is subtracted from the clock period to create an effective clock period. The clock uncertainty is defined in ns, or as a percentage of the clock period. The clock uncertainty defaults to 27% of the clock period. When specifying a value, the default units is ns but % or MHz can also be used.
clock_uncertainty=15%
flow_target

Set the flow target to synthesize either a Vitis kernel (.xo) or a Vivado IP (.xci). The Vitis kernel is used in the Application Acceleration flow, while the Vivado IP can be used in the embedded software design flow, as described in Vitis HLS Flow Overview .

Important: There are differences in the interface definition supported by Vivado IP or Vitis kernels as explained in Introduction to Interface Synthesis.

C-Synthesis Sources

syn.cflags
Defines compilation flags to be applied to all syn.file defined source files for use during synthesis.
syn.cflags=-I../../src/
syn.csimflags

Defines compilation flags to be applied to all syn.file source files for use during C-simulation or RTL/Co-simulation.

syn.file

Specify the file path and name of a source file to be used during synthesis of the HLS component. Multiple files require multiple syn.file statements.

The file paths can be specified as either absolute or relative, where relative paths are relative to the location of the config file, whether inside the HLS component or outside the component. 
syn.file=../../src/dct.cpp
syn.file_cflags
Apply a compilation flag for synthesis to the specified source file. Specify the file path and name first, followed by a comma, followed by the cflags: 
syn.file_cflags=../../src/dct.cpp,-I../../src/
syn.file_csimflags
Apply a compilation flag for simulation to the specified source file. Specify the file path and name first, followed by a comma, followed by the csimflags. 
syn.file_csimflags=../../src/dct.cpp,-Wno-unknown-pragmas
syn.blackbox.file
Specify the JSON file to be used for an RTL blackbox. The information in this file is used by the HLS compiler during synthesis and when running RTL/Co-simulation, as described in Adding RTL Blackbox Functions. 
syn.blackbox.file=../../RTL/fft.json
syn.top
Specifies the name of the function to be synthesized as the top-level function for the HLS component. This can be used to identify the top function in source code where multiple functions are defined. 
syn.top=dct
Important: Any functions called by the top-level function will also become part of the HLS component.

Testbench Sources

tb.cflags arg
Defines compilation flags to be applied to all tb.file defined source files for use during simulation or co-simulation.
tb.cflags=-Wno-unknown-pragmas
tb.file arg

Specify the file path and name of a testbench source file to be used during simulation or co-simulation of the HLS component. Multiple files require multiple tb.file statements.

The file paths can be specified as either absolute or relative, where relative paths are relative to the location of the config file, whether inside the HLS component or outside the component. 
tb.file=../../src/dct_test.cpp
tb.file_cflags arg
Apply a compilation flag for simulation or co-simulation to the specified testbench source file. Specify the file path and name first, followed by a comma, followed by the cflags: 
syn.file_cflags=../../src/dct.cpp,-Wno-unknown-pragmas

Synthesis Output

syn.output.file
Specifies the output file path and name for the exported file. An example command would be: 
syn.output.file=../kernel.xo
syn.output.format

Specifies the exported format of the output generated after synthesis. The supported values are:

  • syn.output.format=rtl: Specifies that the output of synthesis should be just the generated RTL files and not the packaged IP or XO used for downstream processes.
    Tip: The RTL format is useful for development, analysis, and debug of the HLS component. However, to export files you must specify one of the other output formats.
  • syn.output.format=ip_catalog: A format suitable for adding to the Vivado IP catalog.
  • syn.output.format=xo: A format accepted by the v++ compiler for linking in the Vitis application acceleration flow.
  • syn.output.format=syn_dcp: Synthesized checkpoint file for Vivado Design Suite. If this option is used, RTL synthesis is automatically executed. Vivado implementation can be optionally added using vivado.flow=impl
  • syn.output.format=sysgen: Generate an IP and .zip archive for use in System Generator.