Optimizations in Vitis HLS
In the AMD Vitis™
software platform, a kernel defined in the
C/C++ language, or
OpenCL™
C, must be compiled into the
register transfer level (RTL) that can be implemented into the programmable logic of an AMD device. The v++ compiler
calls the Vitis High-Level Synthesis (HLS) tool to
synthesize the RTL code from the kernel source code.
The HLS tool is intended to work with the Vitis IDE project without interaction. However, the HLS tool also provides pragmas that can be used to optimize the design, reduce latency, improve throughput performance, and reduce area and device resource usage of the resulting RTL code. These pragmas can be added directly to the source code for the kernel.
The HLS pragmas include the optimization types specified in the following table.
| Type | Attributes |
|---|---|
| Kernel Optimization | |
| Function Inlining | |
| Interface Synthesis | |
| Task-level Pipeline | |
| Pipeline | |
| Loop Unrolling | |
| Loop Optimization | |
| Array Optimization | |
| Structure Packing |