Running C Simulation - 2023.1 English

Loading Test Bench Files

Like C synthesis, the source files required for simulation can be loaded at the time the HLS component is created. However, you can skip that step at creation and add the test bench files prior to running simulation. It is also possible to change or add to the files used for simulation. This is done in the Testbench sources section of the Config Editor.

Figure 1. HLS Component Testbench Sources

The Testbench sources displays currently added test bench files, and lets you edit, or delete current files, add new files, and add or modify CFLAGS for the test bench.

• Add item: Select this command to add new test bench files to the HLS component. This opens a File Browser, and lets you navigate to and select the files to add.
• Add CFLAGS: You can add compilation flags (CFLAGS) to be applied to all source files, or to be added to specific source files. As shown in the figure above, simply add the flags to the appropriate text entry box for Flags common to all files. To add flags for specific source files, select the source file and select Edit item to add the flags, or modify the file name and path.

[HLS]
tb.file=../../src/in.dat
tb.file=../../src/out.golden.dat
tb.file=../../src/dct_test.cpp
tb.cflags=<cflag>
tb.file_cflags=../../src/dct_test.cpp,<cflag>

Configure the Simulator

You can configure the C simulator prior to running simulation using the C Simulation section of the Config Editor, as shown below.

Figure 2. HLS Component Simulation Settings

These configuration commands let you specify how the simulation should run. The configuration options include:

O

By default the design is compiled with debug information enabled, allowing the compilation to be analyzed and debugged. The Optimizing Compile option uses a higher level of optimization effort when compiling the design, but does not add information required by the debugger. This increases the compile time but should reduce the simulation runtime.

argv

Specify any inputs required by your test bench main() function.

clean

Remove any existing executable and object files from the project before compiling the code.

ldflags

Specifies the options passed to the linker for simulation. This option is typically used to pass include path information or library information for the C/C++ test bench.

mflags

Provides for options to be passed to the compiler for C simulation. This is typically used to speed up compilation.

profile

Enable the creation of the Pre-Synthesis Control Flow.

setup

When this option is specified, the simulation binary will be created in the csim directory of the current HLS component, but simulation will not be executed. Simulation can be launched later from the compiled executable. The default is false, and simulation is run after setup is complete.

[HLS]
csim.profile=true
csim.clean=true
csim.O=true
csim.argv=arg1 arg2

Run Simulation

With the C simulation setup in the config file you are ready to select Run from the Flow Navigator and begin simulation. You can track the progress of simulation in the Output window. The transcript for the synthesis run will have the top function name as <component-name>::c_simulation as shown below.

Figure 3. HLS Component Running Simulation

The simulation run in the Vitis IDE uses the vitis-run --mode hls --csim command as described in vitis-run Command. When the simulation is complete a Summary report is generated which shows the simulation command and the time stamp of the run.