The syn.op
command lets you
configure the default implementation style, latency, and precision for different
operators used for the HLS component. You can add multiple syn.op
commands to a config file to specify the details of different operators. If an
operator is not specified then the tool determines the default values for the
component.
You can override the default settings specified by the syn.op
command by using the syn.directive.bind_op command for specific
variables.
 syn.op

The syntax for the
syn.op
command is as follows:syn.op=op:mul impl:dsp syn.op=op:add impl:fabric latency:6 syn.op=op:fmacc precision:high syn.op=op:hdiv latency:5

syn.op=
: Starts the command 
op:<operator>
: Specifies theop
keyword followed by the operator being defined. The supported operators include:
mul
: integer multiplication operation 
add
: integer add operation 
sub
: integer subtraction operation 
fadd
: single precision floatingpoint add operation 
fsub
: single precision floatingpoint subtraction operation 
fdiv
: single precision floatingpoint divide operation 
fexp
: single precision floatingpoint exponential operation 
flog
: single precision floatingpoint logarithmic operation 
fmul
: single precision floatingpoint multiplication operation 
frsqrt
: single precision floatingpoint reciprocal square root operation 
frecip
: single precision floatingpoint reciprocal operation 
fsqrt
: single precision floatingpoint square root operation 
dadd
: double precision floatingpoint add operation 
dsub
: double precision floatingpoint subtraction operation 
ddiv
: double precision floatingpoint divide operation 
dexp
: double precision floatingpoint exponential operation 
dlog
: double precision floatingpoint logarithmic operation 
dmul
: double precision floatingpoint multiplication operation 
drsqrt
: double precision floatingpoint reciprocal square root operation 
drecip
: double precision floatingpoint reciprocal operation 
dsqrt
: double precision floatingpoint square root operation 
hadd
: half precision floatingpoint add operation 
hsub
: half precision floatingpoint subtraction operation 
hdiv
: half precision floatingpoint divide operation 
hmul
: half precision floatingpoint multiplication operation 
hsqrt
: half precision floatingpoint square root operation 
facc
: single precision floatingpoint accumulate operation 
fmacc
: single precision floatingpoint multiplyaccumulate operation 
fmadd
: single precision floatingpoint multiplyadd operation
Tip: Comparison operators, such asdcmp
, are implemented in LUTs and cannot be implemented outside of the fabric, or mapped to DSPs, and so are not configurable with thesyn.op
orsyn.directive.bind_op
commands. 

impl:<value>
: Specifies the implementation (impl
) keyword followed by the value for the specified operator. Whenimpl
is not specified, the default is for the tool to determine the best implementation for a given operator. Supported values include:
all
: All implementations. This is the default setting. 
dsp
: Use DSP resources 
fabric
: Use nonDSP resources 
meddsp
: Floating Point IP Medium Usage of DSP resources 
fulldsp
: Floating Point IP Full Usage of DSP resources 
maxdsp
: Floating Point IP Max Usage of DSP resources 
primitivedsp
: Floating Point IP Primitive Usage of DSP resources 
auto
: enable inference of combinedfacc
fmacc
fmadd
operators 
none
: disable inference of combinedfacc
fmacc
fmadd
operators


latency:<value>
: Specifies thelatency
keyword followed by the value. Defines the default latency for the binding of the operator to the implementation resource. The valid value range varies for each implementation (impl
) of the operation. The default is 1, which lets the tool apply the standard latency for the implementation resource.Tip: You can specify the latency for a specific operation without specifying the implementation. This leaves the tool free to choose the implementation while managing the latency. 
precision:<value>
: Used for floating point operators (facc
,fmacc
, andfmadd
), this specifies theprecision
keyword followed by one of the following:
low
: Use a low precision (60 bit and 100 bit integer) accumulation implementation when available. This option is only available on certain nonAMD Versalâ„¢ devices, and can cause RTL/CoSim mismatches due to insufficient precision with respect to C++ simulation. However, it can always be pipelined with an II=1 without source code changes, though it uses approximately 3X the resources ofstandard
precision floating point accumulation. 
high
: Use high precision (one extra bit) fused multiplyadd implementation when available. This option is useful for highprecision applications and is very efficient on Versal devices, although it can cause RTL/CoSim mismatches due to the extra precision with respect to C++ simulation. It uses more resources thanstandard
precision floating point accumulation. 
standard
: standard precision floating point accumulation and multiplyadd is suitable for most uses of floatingpoint, and is the default setting. It always uses a true floatingpoint accumulator that can be pipelined with II=1 on Versal devices, and II that is typically between 3 and 5 (depending on clock frequency and target device) on nonVersal devices.

