Building and Running an HLS Component - 2023.1 English

In an HLS component, the AMD Vitis™ tool synthesizes a C or C++ function into RTL code for implementation in the programmable logic (PL) region of an AMD Versal™ adaptive SoC, AMD Zynq™ MPSoC, or AMD FPGA device. An HLS component can be used to develop and export:

• Vivado IP to be integrated into hardware designs using the Vivado Design Suite and the Embedded Software Development flow
• Vitis kernels for use in the Vitis application acceleration development flow

The following are the steps for the development of the C++ function.

1. Architect the algorithm based on Design Principles
2. (C-Simulation) Verify the C/C++ Code with a C test bench
3. (C-Synthesis) Generate the RTL from source code
4. (Co-Simulation) Verify the RTL module with the C test bench and RTL logic simulation
5. (Analyze) Review and analyze the HLS synthesis reports and co-simulation reports
6. Repeat previous steps until performance goals are met

The HLS component implements the design based on the target flow, default tool configuration, configuration commands, and any optimization pragmas or directives you specify. The following sections describe creating and building the HLS component.