The syn.interface
commands
configure the default interface settings applied to the HLS component. These
settings can be overridden for specific top-level interface ports using syn.directive.interface
.
- syn.interface.clock_enable
-
Add a clock-enable port (
ap_ce
) to the design. The clock enable prevents all clock operations when it is active low, and disables all sequential operations. The default is false.syn.interface.clock_enable=1
- syn.interface.default_slave_interface
-
Specify the default slave interface. The two modes are
s_axilite
andnone
. The default iss_axilite
.syn.interface.default_slave_interface=none
- syn.interface.m_axi_addr64
-
Enable 64-bit addressing for all
m_axi
interfaces. This is enabled by default. When disabled, them_axi
interfaces uses 32-bit addressing.syn.interface.m_axi_addr64=1
- syn.interface.m_axi_alignment_byte_size
-
Specify default alignment byte size for all
m_axi
interfaces. The default when this option is not specified is 64 bytes for Vitis kernel flow, or 1 byte for Vivado IP flow as described in Defaults of Vivado and Vitis Flows.syn.interface.m_axi_alignment_byte_size=16
Tip: A value of 0 is not valid. - syn.interface.m_axi_auto_id_channel
-
Enable automatic assignment of channel IDs for
m_axi
interfaces. This is disabled by default. Refer to AXI4 Master Interface for additional information.syn.interface.m_axi_auto_id_channel=1
- syn.interface.m_axi_auto_max_ports
-
Enable automatic creation of separate
m_axi
interface adapters for each argument or port on the interface. This is disabled by default, reducing them_axi
interfaces to minimum needed. Refer to M_AXI Bundles for more information.syn.interface.m_axi_auto_max_ports=1
- syn.interface.m_axi_buffer_impl
-
Specify the implementation resource for all buffers internal to the
m_axi
adapters. The choices areauto
,lutram
,bram
,uram
. The default isbram
.syn.interface.m_axi_buffer_impl=lutram
- syn.interface.m_axi_conservative_mode
-
Configure all
m_axi
adapters to work in conservative mode, waiting to issue a write request until the associated write data is entirely available (typically, buffered into the adapter or already emitted). It uses a buffer inside the MAXI adapter to store all the data for a burst (both in case of reading and writing). This feature is enabled by default, and might slightly increase write latency but can resolve deadlock due to concurrent requests (read or write) on the memory subsystem. Disable conservative mode by setting it tofalse
.syn.interface.m_axi_conservative_mode=0
- syn.interface.m_axi_flush_mode
-
Configure all
m_axi
adapters to be flushable, writing or reading garbage data if a burst is interrupted due to pipeline blocking (missing data inputs when not in conservative mode or missing output space). This is disabled by default.syn.interface.m_axi_flush_mode=1
- syn.interface.m_axi_latency
-
Globally specify the expected latency of the
m_axi
interface, allowing the design to initiate a bus request a number of cycles (latency) before the read or write is expected. The default value is 64 for the Vitis Kernel flow, and 0 for the Vivado IP flow, as described in Defaults of Vivado and Vitis Flows.syn.interface.m_axi_latency=5
- syn.interface.m_axi_max_bitwidth
-
Specifies the maximum bitwidth for the
m_axi
interfaces data channel. The default is 1024 bits. The specified value must be a power-of-two, between 8 and 1024. Note that this decreases throughput if the actual accesses are bigger than the required interface, as they will be split into a multi-cycle burst of accesses.syn.interface.m_axi_max_bitwidth=128
- syn.interface.m_axi_max_read_burst_length
-
Specifies a global maximum number of data values read during a burst transfer for all
m_axi
interfaces. The default is 16.syn.interface.m_axi_max_read_burst_length=12
- syn.interface.m_axi_max_widen_bitwidth
-
Enable automatic port width resizing to widen bursts for the
m_axi
interface, up to the chosen bitwidth. The specified value must be a power of 2 between 8 and 1024, and must align with the-m_axi_alignment_size
. The default value is 512 for the Vitis Kernel flow, and 0 for the Vivado IP flow, as described in Defaults of Vivado and Vitis Flows.syn.interface.m_axi_max_widen_bitwidth=64
- syn.interface.m_axi_max_write_burst_length
-
Specifies a global maximum number of data values written during a burst transfer for all
m_axi
interfaces. The default is 16.syn.interface.m_axi_max_write_burst_length=12
- syn.interface.m_axi_min_bitwidth
-
Specifies the minimum bitwidth for
m_axi
interfaces data channel. The default is 8 bits. The value must be a power of 2, between 8 and 1024. Note that this does not necessarily increase throughput if the actual accesses are smaller than the required interface.syn.interface.m_axi_min_bitwidth=64
- syn.interface.m_axi_num_read_outstanding
-
Specifies how many read requests can be made to the
m_axi
interface without a response, before the design stalls. This implies internal storage in the design, and a FIFO of size:num_read_outstanding*max_read_burst_length*word_size
The default value is 16.syn.interface.m_axi_num_read_outstanding=8
- syn.interface.m_axi_num_write_outstanding
-
Specifies how many write requests can be made to the
m_axi
interface without a response, before the design stalls. This implies internal storage in the design, and a FIFO of size:num_write_outstanding*max_write_burst_length*word_size
The default value is 16.syn.interface.m_axi_num_write_outstanding=8
- syn.interface.m_axi_offset
-
Specify the default offset mechanism for all
m_axi
interfaces. The options are:-
off
: No offset port is generated. -
slave
: Generates an offset port and automatically maps it to ans_axilite
interface. This is the default value. -
direct
: Generates a scalar input offset port for directly passing the address offset into the IP through the offset port.
syn.interface.m_axi_offset=slave
-
- syn.interface.register_io
-
Globally enables registers for all scalar inputs, outputs, or all scalar ports on the top function (arrays are always registered). The options are
off
,scalar_in
,scalar_out
,scalar_all
. The default isoff
.syn.interface.register_io=scalar_out
- syn.interface.s_axilite_auto_restart_counter
-
Enables the auto-restart behavior for kernels. Use 1 to enable the auto-restart feature, or 0 to disable it which is the default. When enabled, the tool establishes the auto-restart bit in the
ap_ctrl_chain
control protocol for thes_axilite
interface. For more information refer to Auto-Restarting Mode.syn.interface.s_axilite_auto_restart_counter=1
- syn.interface.s_axilite_data64
-
Enable 64 bit data width for
s_axilite
interface. Use 1 to enable 64 bit data width and 0 to disable it. The default is 32 bit data width.syn.interface.s_axilite_data64=1
- syn.interface.s_axilite_interrupt_mode
-
Specify the interrupt mode for
s_axilite
interface to be Clear on Read (cor
) or Toggle on Write (tow
). Clear on Read interrupt can be completed in a single transaction, whiletow
requires two.Tow
is the default interrupt mode.syn.interface.s_axilite_interrupt_mode=cor
- syn.interface.s_axilite_mailbox
- Enables the creation of a mailboxes for non-stream non-stable
s_axilite
arguments. The mailbox feature is used in the setting and management of auto-restart kernels as described in Auto-Restarting Mode. - syn.interface.s_axilite_status_regs
-
Enables exposure of ECC error bits in the
s_axilite
register file via two clear-on-read (COR) counters per BRAM or URAM with ECC enabled. Options areecc
to enable oroff
to disable the feature. The default is disabled.syn.interface.s_axilite_status_regs=ecc
- syn.interface.s_axilite_sw_reset
-
Enable SW reset in
s_axilite
adapter.syn.interface.s_axilite_sw_reset=1