Using the GCLK_DESKEW Property on a Clock Net - 2024.2 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2024-12-18
Version
2024.2 English

You can use the GCLK_DESKEW property to control calibrated deskew for a clock net. By default it is OFF. For devices that support calibrated deskew, enabling calibrated deskew lowers intra-clock (and same MBUFG driver inter-clock) skew but results in longer insertion delays.

For some clocking topologies, it is more important to minimize insertion delay, while others, a lower skew is more beneficial. Typically, designs that benefit from lower insertion delay have:

  • I/O timing paths
  • Inter-clock timing paths

Designs that benefit from lower skew typically have:

  • Higher performance clocks over 350 MHz
  • Clocks with a high number of clock loads

For more information on default calibrated deskew settings for different Versal devices, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).

To enable calibrated deskew, you must set the GCLK_DESKEW property on the net segment directly driven by the clock buffer. Following is an example:

set_property GCLK_DESKEW CALIBRATED [get_nets -of [get_pins clkgen/BUFG_clkout2_inst/O]]