You can use the CLOCK_DELAY_GROUP constraint to match the insertion delay of
multiple, related clock networks driven by different clock buffers. Designers commonly
use this constraint to minimize skew on synchronous CDC timing paths. These paths are
between clocks originating from the same MMCM, XPLL, DPLL, or GT source. The following
example shows the clk1_net and clk2_net clock nets, which are directly driven by the clock buffers:
set_property CLOCK_DELAY_GROUP grp12 [get_nets {clk1_net clk2_net}]If possible, use the MBUFG* cells to minimize skew on synchronous CDC timing paths or when matching the insertion delay of multiple related clock networks. When using a single MBUFG* cell, do not use the CLOCK_DELAY_GROUP constraint. When matching the insertion delay of a clock network driven by an MBUFG* cell, use the CLOCK_DELAY_GROUP constraint. This constraint helps match the delay to a clock network of another global clock buffer. The following example shows how to use the CLOCK_DELAY_GROUP constraint.
set_property CLOCK_DELAY_GROUP mbufGrp [get_nets -of [get_pins MBUFGCE_inst/O*]]
set_property CLOCK_DELAY_GROUP mbufGrp [get_nets -of [get_pins BUFGCE_gated_inst/O]]