Kernel Interfaces - 2024.2 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2024-12-18
Version
2024.2 English

AMD strongly recommends creating PL kernels with the following interfaces:

  • At least one clock and one reset
  • Standard AXI interfaces:
    • Memory mapped AXI4 interface for memory mapped transfers over the NoC
    • AXI4-Stream for connections to other PL kernels, AI Engine graphs, or streaming platform ports
    • AXI4-Lite for control by the PS (software controllable kernels only)

For more information, see Mapping Kernel Ports to Memory in the Data Center Acceleration using Vitis (UG1700).

Working with standard AXI interfaces enables design automation by the Vitis tools flow and reduces manual and error-prone tasks. However, it is also possible for PL kernels to have non-AXI interfaces. In this case, you need to manually and explicitly connect each of the non-AXI signals during the Vitis linking phase using the connectivity.connect option, as described in --connectivity Options in the Vitis Reference Guide (UG1702).