Example One - 2024.1 English

Use a virtual clock with a period greater or equal to the target maximum delay for the feed-through path, and apply max input and output delay constraints as follows:

create_clock -name vclk -period 10
set_input_delay -clock vclk <input_delay_val> [get_ports din] -max
set_output_delay -clock vclk <output_delay_val> [get_ports dout] -max

where

input_delay_val(max) + feedthrough path delay (max) + output_delay_val(max)
<= vclk period.

In this example, only the maximum delay is constrained.