Clock Primitives - 2024.1 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2024-06-19
Version
2024.1 English

Most clocks enter the device through a global clock-capable I/O (GCIO) pin. In horizontal XPIO banks, these clocks directly drive the clock network via a global clock buffer or are transformed by an MMCM, XPLL, or DPLL located in the clock management tiles (CMTs) of the XPIO bank. For devices with columnar HDIO banks, the clocks drive the clock network via a global clock buffer or are transformed by DPLL located in the CMT of the HDIO bank for devices with this feature.

Each horizontal XPIO bank contains the following clocking resources:

  • Clock generation blocks
    • 1 MCMM
    • 2 XPLLs
    • 1 DPLL
  • Global clock buffers
    • 24 BUFGCEs/MBUFGCEs
    • 8 BUFGCTRLs/MBUFGCTRLs
    • 4 BUFGCE_DIVs/MBUFGCE_DIVs
Note: Clocking resources in XPIO banks that exist in the corner of Versal devices are limited and have inaccessible resources such as BUFGCTRLs and BUFGCE_DIVs. To use BUFGCTRLs and BUFGCE_DIVs for clocks sourced from a corner bank, it might be necessary to use a cascaded clocking topology, as described in Cascaded Clock Buffers. Clocking resources in XPIO banks that have unbonded I/Os are available for use. For more information on XPIO corner bank restrictions, see this link in the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).

For devices with columnar HDIO banks, each bank contains the following clocking resources:

  • Clock generation blocks
    • 1 DPLL
  • Global clock buffers
    • 4 BUFGCEs/MBUFGCEs
Note: DPLL is not available in HDIO banks for VC1902, VC1802, and VM1802 devices.

Each gigabit transceiver (GT*_QUAD) clock region column contains the following clocking resources:

  • Clock generation blocks
    • 1 DPLL
  • Global clock buffers
    • 24 BUFG_GTs/MBUFG_GTs

The following table provides a summary of the Versal device clock buffers.

Table 1. Versal Device Clock Buffers
Versal Device Clock Buffer Leaf-Level Clock Division Support Location Description
BUFGCE Yes using MBUFGCE XPIO and HDIO banks The most commonly used buffer is the BUFGCE, which is a general clock buffer with a clock enable/disable feature.
BUFGCE_DIV Yes using MBUFGCE_DIV XPIO banks The BUFGCE_DIV is useful when a simple division of the clock is required. This clock buffer is considered easier to use and more power efficient than using an MMCM or PLL for simple clock division.
BUFGCTRL Yes using MBUFGCTRL XPIO banks The BUFGCTRL can be instantiated as a BUFGMUX and is generally used when multiplexing two or more clock sources to a single clock network. As with the BUFGCE and BUFGCE_DIV, this clock buffer can drive the clock network for either regional or global clocking.
BUFG_GT Yes using MBUFG_GT GT*_QUAD columns When using clocks generated by GTs, the BUFG_GT clock buffer allows connectivity to the global clock network. In most cases, the BUFG_GT is used as a regional buffer with its loads placed in one or two adjacent clock regions. The BUFG_GT has built-in dynamic clock division capability that you can use in place of an MMCM for clock rate changes.
BUFG_PS Yes using MBUFG_PS Vertical clock column adjacent to PS The BUFG_PS is a simple clock buffer with one clock input (I) and one clock output (O). This clock buffer is a resource for the PS and provides access to the PL clock routing resources for clocks from the processor into the PL. There are up to 12 BUFG_PS buffers available.
BUFG_FABRIC No NoC columns The BUFG_FABRIC is driven by the PL and used for routing high-fanout, non-clock nets, which allows a signal from the PL routing resources to be brought onto the clock network. However, this clock buffer is not for global clocking.