The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 12/18/2024 Version 2024.2 | |
| Design Planning for Key IP Blocks | Updated GT IP description. |
| Design Planning Considerations for Segmented Configuration | Added new section. |
| Recommendations for Designing with Versal Device IP | Updated IP description. |
| Using Modular NoC in RTL Designs | Added new section. |
| Decomposing Deeper Memory Configurations for Improved Area | Added new section. |
| Using the GCLK_DESKEW Property on a Clock Net | Updated section. |
| Using the CLOCK_LOW_FANOUT Constraint | Updated section. |
| Using the CLOCK_ROUTE_GUIDE Constraint | Added VERTICAL_COLUMN description. |
| Optimal CLOCK_ROOT Placement | Added CLOCK_ROOT description. |
| Super Long Line (SLL) Routes | Updated code description. |
| Incremental Implementation Flows | Removed section. |
| 06/19/2024 Version 2024.1 | |
| SLR Utilization Example | Updated description and figures. |
| Floorplanning Constraints for Dynamic Function eXchange | Updated Pblock description. |
| Floorplanning Visualization for Dynamic Function eXchange | Added section. |