Design Planning Considerations for AI Engine and Programmable Logic Integration - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2023-11-15
Version
2023.2 English

The development of Versal adaptive SoC designs can be achieved through a combination of hardware development using Vivado tools and software development using Vitis tools. There are various design methodologies available for design development and the selection of a methodology should be based on the specific requirements of the design flow. These methodologies can significantly improve the efficiency of the design development flow. AMD recommends developing the hardware design in Vivado. If a hardware platform is available, it can be used in Vitis to develop the software components. You can develop Versal adaptive SoC designs using either the Vitis Integrated flow or Vitis Export to Vivado flow.

AMD recommends using the Vitis Export to Vivado flow when you are done with the AI Engine and HLS software component development and would like to continue the hardware development exclusively in Vivado. This flow enables you to complete the hardware design development and verification in Vivado.

  1. For the Vitis Export to Vivado flow, the steps for the flow are as follows:
    1. Create the hardware design using Vivado.
    2. Export the extensible xsa from Vivado.
    3. Compile kernels (AI Engine/HLS) in Vitis to generate libadf.a and .xo.
    4. Generate the .vma file by linking compiled outputs, extensible.xsa, and config files with switch --export_archive. v++ --link does not run synthesis and implementation.
    5. Import the .vma into Vivado.
    6. Perform the design modifications in Vivado.
    7. Run the synthesis and implementation.
    8. Generate the fixed.xsa using write_hw_platform -fixed.
    9. Generate the xclbin from fixed.xsa (Vivado generated) using the v++ --package.
    10. Take the design to hardware.

    For more information on the Vitis Export to Vivado flow, see this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

  2. For the Vitis Integrated flow, this is recommended for hardware design platforms that have been built in Vivado. This flow enables you to use the platform and plug in AI Engine/HLS software components of the application. This flow is typically useful when the hardware development is complete and software components need to be added or modified. The steps for the flow are as follows:
    1. Create the hardware design using Vivado.
    2. Export the extensible xsa from Vivado.
    3. Compile kernels (AI Engine/HLS) in Vitis to generate libadf.a and .xo.
    4. Generate the fixed.xsa by linking compiled outputs, extensible.xsa, and config files. Synthesis and implementation runs in this stage. Fixed xsa is generated by Vitis after closing all design runs.
    5. Generate the xclbin from the fixed.xsa (Vitis generated) using the v++ --package.
    6. Take the design to hardware.

    For more information on report generation, see this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

  3. For the Vitis Design Development without a platform, this flow is recommended for targeting devices in which evaluation boards or platforms have not been released by AMD. Using this flow, you can start the software development of AI Engine/HLS components of your application. This flow does not require the use of xsa (generated from Vivado) for your software development. The steps for the flow are as follows:
    1. Compile AI Engine with the --part.
    2. Generate the XSA using v++ --link --part ….
    3. Compile the HLS with generate XSA.
    4. Generate the fixed.xsa by linking compiled outputs, extensible.xsa, and config files. Synthesis and implementation runs in this stage. Fixed xsa is generated by Vitis after closing all design runs.
    5. Generate the xclbin from the fixed.xsa (Vitis generated) using the v++ --package.
    6. Take the design to hardware.

    For more information, see the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).