Using the CLOCK_ROUTE_GUIDE Constraint - 2024.2 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2024-12-18
Version
2024.2 English

The CLOCK_ROUTE_GUIDE is a STRING property that can be applied to clock pin objects. This property allows you to define the route of a specified clock net to a load pin in the XPIO. The CLOCK_ROUTE_GUIDE property can be used to closely match the clock routing and delay for a clock net that drives XPIO load pins such as MMCM/CLKFB1_DESKEW pins. Valid values are CMT_ROW, BUFDIV_LEAF, VERTICAL_COLUMN, and ANY.

Note: This property only applies to the XPIO clock loads.

The following table summarizes the different CLOCK_ROUTE_GUIDE constraint values, use, and behavior.

Table 1. Versal Device CLOCK_ROUTE_GUIDE Constraint Summary
Value Use Behavior
CMT_ROW A horizontal route only contained in the XPIO clock region row

Example:

set_property CLOCK_ROUTE_GUIDE CMT_ROW [get_pins myHier/myBUFG/I]
 When CLOCK_ROUTE_GUIDE == CMT_ROW, the clock routing should be contained in the XPIO clock region row.
BUFDIV_LEAF When routing to use a BUFDIV_LEAF through BLI when reaching the XPIO

Example:

set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins myHier/myBUFG/I]
 When CLOCK_ROUTE_GUIDE == BUFDIV_LEAF, the clock routing should go through the BUFDIV_LEAF and the BLI.
VERTICAL_COLUMN When routing a clock using vertical routing and distribution to match insertion delay to a fabric clock with the same root

Example:

set_property CLOCK_ROUTE_GUIDE VERTICAL_COLUMN [get_pins MMCME5_inst/CLKFBIN]
 When CLOCK_ROUTE_GUIDE == VERTICAL_COLUMN, the clock routing should take the vertical route to the clock root in the fabric clock region and down to the XPIO clock region through the vertical distribution.
ANY When routing to use an ANY possible route when reaching the XPIO

Example:

set_property CLOCK_ROUTE_GUIDE ANY [get_pins myHier/myBUFG/I]
 When CLOCK_ROUTE_GUIDE == ANY, the clock routing can go through ANY permitted nodes.

Here is an example code for BUFDIV_LEAF:

set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins sample_clk_mmcm/inst/clock_primitive_inst/MMCME5_inst/CLKFB1_DESKEW]

The following figure shows the clock routing going through the BUFDIV_LEAF and the BLI for the XPLL feedback path.

Figure 1. CLOCK_ROUTE_GUIDE Constraint Set to BUFDIV_LEAF

Here is an example code for CMT_ROW:

set_property CLOCK_ROUTE_GUIDE CMT_ROW [get_pins receiver_inst/xpll_fifo_wr_clk/CLKFB1_DESKEW]

The following figure shows the clock routing solely contained in the XPIO Bank for the MMCM feedback path.

Figure 2. CLOCK_ROUTE_GUIDE Constraint Set to CMT_ROW

Here is an example code for VERTICAL_COLUMN:

set_property CLOCK_ROUTE_GUIDE VERTICAL_COLUMN [get_pins MMCME5_inst/CLKFBIN]

The following figure shows the clock routing up and down the vertical column for the MMCM feedback path.

Figure 3. CLOCK_ROUTE_GUIDE Constraint Set to VERTICAL_COLUMN

To use the CLOCK_ROUTE_GUIDE, enter the constraint and assign the value depending on desired behavior. The current supported values are CMT_ROW, BUFDIV_LEAF, and ANY.

For example, when you want a horizontal route only contained in the XPIO bank where the clock management tiles are aligned in a row:

set_property CLOCK_ROUTE_GUIDE CMT_ROW [get_pins myHier/myBUFG/I]

For example, when you want the route to use a BUFDIV_LEAF through BLI when reaching the XPIO:

set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins myHier/myBUFG/I]