Synchronous CDC - Synchronous CDC - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

The design includes synchronous CDC paths between clocks from the same MMCM/XPLL/DPLL. You can use specific techniques to control clock insertion delays. These techniques also help manage skew and slack on those paths.

Important: The CDC paths are between clocks from different MMCM/XPLL/DPLLs. The clock insertion delays across the MMCM/XPLL/DPLLs are more difficult to control. In this case, AMD recommends that you treat these clock domain crossings as asynchronous and make design changes accordingly.
Important: Refer to this link in the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003). Ensure the configuration of the primitive allows safe timing between the clocks. This applies if the CDC paths are between the input clock and the output clock. It also applies if the CDC paths are between two or more output clocks of a MMCM or XPLL primitive. For DPLL, refer to this link in Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).

Two clocks time a path. These clocks come from different output pins of the same MMCM/XPLL/DPLL. The MMCM/XPLL/DPLL phase error adds to the clock uncertainty for the path. For designs using high clock frequencies, the phase error can cause issues with timing closure both for setup and hold.

The following figure shows an example of paths both with and without the phase error. Path 1 is a CDC path clocked by two buffers connected to the same MMCM output and does not include the phase error. Path 2 is clocked by two clocks that originate from two different MMCM outputs and does include the phase error.

Figure 1. MMCM and Phase Error

Two synchronous clocks from the same MMCM/XPLL/DPLL have a simple period ratio, such as /2 /4 /8. You can prevent phase error between the two clock domains. Use a single MMCM/XPLL/DPLL output connected to a single MBUFGCE or connected to two BUFGCE_DIV buffers.

The MBUFGCE cell can perform simple clock division of (/1 /2 /4 /8) and simple clock multiplication (*2). The BUFGCE_DIV buffer can perform the simple clock division (/1 /2 /4 /8). The BUFGCE_DIV can also provide other division ratios (/3 /5 /6 /7) but this requires modifying the clock duty cycle and making mixed edge timing paths more challenging.

The following figure shows a single MBUFGCE cell. It divides the CLKOUT0 clock by 1 on the O1 pin and by 2 on the O2 pin. The MBUFGCE cell does not require any additional clock constraints on the logical output nets. The net routes on a single clock track until it reaches the leaf-level dividers.

Figure 2. Synchronous CDC with MBUFGCE Connected to One MMCM Output

The following figure shows two BUFGCE_DIVs that divide the CLKOUT0 clock by 1 and by 2, respectively.

Figure 3. Synchronous CDC with BUFGCE_DIVs Connected to an MMCM Output
Note: AMD recommends using the same clock buffer for both synchronous clocks. The BUFGCE and BUFGCE_DIV do not have the same cell delays. Use two BUFGCE or two BUFGCE_DIV buffers.
Important: Set the BUFGCE_DIVIDE property to a value greater than 1 to ensure safe timing between parallel BUFGCE_DIV cells. Both buffers must use the same enable signal (CE) and the same reset signal (RST). Otherwise, the hardware can phase shift the divided clocks relative to each other, and the Vivado tools do not report it.

Set the same CLOCK_DELAY_GROUP property value on the nets driven by the clock buffers. This automatically balances several clocks from the same MMCM or PLL. Following are additional recommendations:

  • Avoid setting the CLOCK_DELAY_GROUP constraint on too many clocks, because this stresses the clock placer resulting in suboptimal solutions or errors.
  • Use the GCLK_DESKEW constraint with value OFF in combination with the CLOCK_DELAY_GROUP constraint to minimize and match insertion delay on clock nets.
  • Review the critical synchronous CDC paths in the Timing Summary Report to determine which clocks you must delay match to meet timing.
  • Limit the use of the CLOCK_DELAY_GROUP on groups of synchronous clocks with tight requirements and with identical clocking topologies.
    Important: AMD recommends using the Clocking Wizard for creating optimal clocking structures, which use a mix of BUFGCEs and BUFGCE_DIVs along with related clock grouping constraints.