The clock edges used in the I/O constraint must reflect the data sheet of the
external device connected to the device. By default, the set_input_delay and set_output_delay
commands define a delay constraint relative to the rising reference clock edge. You must
use the clock_fall option to specify a delay relative
the falling clock edge. You can specify separate constraints for delays related to both
rising and falling clock edges. Use the add_delay option
with the second constraint on a port.
In most cases, the I/O reference clock edges correspond to the clock edges. Those internal clock edges latch or launch the I/O data inside the device. Analyze the I/O timing paths to review the clock edges used. Verify that these edges correspond to the actual hardware behavior.
If you mistakenly use a rising clock edge as the reference clock for an I/O path, an issue occurs. Internally, the path relates only to the falling clock edge. As a result, the tool applies a ½‑period requirement, which makes timing closure more difficult.