Adding Multicycle Path Constraints - Adding Multicycle Path Constraints - 2026.1 English - UG1387

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2026-07-22
Version
2026.1 English

Multicycle path exceptions must reflect the design functionality. They must be applied on paths without an active clock edge at every cycle. This applies to either the source clock, the destination clock, or both clocks.

The path multiplier expresses in terms of clock cycles. It uses the source clock when you use the -start option. It uses the destination clock when you use the -end option. This is particularly convenient for modifying the setup and hold relationships between the startpoint and endpoint independently of the clock period value.

The setup relationships always tie to the hold ones. Consequently, in most cases, the hold relationship also needs to be separately adjusted after the setup one is modified. This is why you need a second constraint with the -hold option. The main exception to this rule is for synchronous CDC paths between phase-shifted clocks: only setup needs to be modified.