The following figure shows the Versal HBM HBM stacked silicon interconnect device. Unlike UltraScale+ HBM devices, the HBM stacks are at the top of the device in yellow, HNoC is highlighted in green, and VNoC highlighted in red. Modules directly connected to the HBM interface should be considered floorplan in the top SLR (adjacent to HBM stacks). This avoids SLR crossing and improve routability and timing closure. Also, perform a capacity check for the modules in the top SLR with Pblock statistics. If you have many HBM interfaces routing over the next SLRs, then the long line routing demands would be high in the top adjacent SLR. This might not have enough routing resources for the local logic in the SLR, so anticipate this and try to reduce the local logic to avoid any routing congestion.
