Multi-Clock Buffer (MBUFG) - 2024.1 English

MBUFGs are clocking primitives that allow you to take advantage of the leaf-level clock dividers driven by the local horizontal clock distribution tracks in Versal devices. The leaf-level division results in the use of only one global clock routing resource providing less clock track resource utilization, improved power efficiency, and improved skew between synchronous clock domains. The MBUFG primitives (MBUFGCE, MBUFGCE_DIV, MBUFG_GT, MBUFGCTRL and MBUFG_PS) have four outputs (O1, O2, O3, O4) that configure a clock divider setting of 1, 2, 4, and 8, respectively, for any leaf clock divider driving the clocking loads connected to the MBUFG primitive. For more information on how the MBUFG primitives can help to reduce the high skew between synchronous clock domains, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).

To use the MBUFG primitives in your design instead of the standard BUFG primitives, select the MBUFG primitives when running the Versal adaptive SoC Clocking Wizard. The MBUFG primitives are only available when the output frequencies are multiple to each other by a factor of 2, 4, or 8. For more information, see this link in the Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321).

The following figure shows logical and physical implementation views of a MBUFG-driven clocking network. The BUFDIV_LEAF primitives are not represented in the logical netlist but are route-through primitives that are configured by the Vivado router. The CLRB_LEAF input on the MBUFG primitives can be used to asynchronously reset the BUFDIV_LEAF dividers. A signal connected to the MBUFG CLRB_LEAF pin is automatically routed to its connected BUFDIV_LEAF CLR_B pin. Because only the 1x clock is routed on the global clock routing and distribution tracks, MBUFG-driven clocks preserve clocking resources. In addition, the common node for paths that are clocked by two output clocks of the same MBUFG is typically much closer to the driver and the load, reducing clock skew and easing timing closure.

Figure 1. MBUFGCE Logical and Physical View

On device startup, the BUFDIV_LEAF clock dividers are reset, and the MBUFG output clocks start up in the High state. In the following cases, special handling is required to ensure that the BUFDIV_LEAF dividers are reset to their startup state before the MBUFG receives an input clock or is enabled again:

• If the MBUFG clock buffer or a clock modifying block driving an MBUFG is reset during device operation
• If the clock driving the MBUFG is violating the minimum pulse width specification after device startup (that is, clock modifying block is not locked)
• If the MBUFG-driven clock network is part of a reconfigurable partition

To reset the BUFDIV_LEAF buffers, the CLRB_LEAF pin of the MBUFG must be asserted Low. To ensure proper device operation, the user logic must stop the MBUFG clock before the CLRB_LEAF pin is asserted Low and hold the clock inactive for a predetermined amount after the CLRB_LEAF signal is deasserted High. The time to hold the clock inactive after the CLRB_LEAF signal is deasserted must be greater than the maximum pin delay time that the router reports for routing the signal connected to the MBUFG CLRB_LEAF pin to the BUFDIV_LEAF CLR_B pins. The router reports this time in an INFO message as shown in the following example. A 10 ns delay is sufficient in most cases to satisfy the CLRB_LEAF net route delay.

INFO: [Route 35-3345] MBUFG*/CLRB_LEAF net route delay summary. Please
ensure that the wait time between de-asserting the CLRB_LEAF signal to 
each MBUFG and enabling the MBUFG output clocks is greater than the 
delay listed in the table below.
+------------------+-------------+--------------------+--------------------+
| MBUFG Cell       | Site        | CLRB_LEAF Net Name | Max Pin Delay (ns) |
+------------------+-------------+--------------------+--------------------+
| U_engine/bufg_fx | BUFGCE_X3Y0 | U_engine/p_1_out   | 2.252              |
+------------------+-------------+--------------------+--------------------+

When using the Clocking Wizard IP, a circuit to meet this reset requirement is added automatically. For more information, see the Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321).

The following figure shows the timing relationship required between the MBUFGCE_DIV CLRB_LEAF and CE signal assertion after CLR has been asserted. The CE signal is held Low to stop the clock until the CLRB_LEAF signal has propagated to all of the BUFDIV_LEAF CLR_B pins. In this example, the CE_TYPE property of the MBUFGCE_DIV is set to SYNC.

Figure 2. Timing Relationship Between Asserting CLRB_LEAF and CE Signals When CLR is Asserted on an MBUFGCE_DIV

You can use the Clock Utilization Report in the Vivado IDE to visually analyze clocking resource utilization and clock routing. The following figure shows the clock resource utilization per clock region overlaid in the Device window. For more information on this report, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Figure 3. Clock Utilization Report

For more information on the BUFGCE, MBUFGCE, BUFGCE_DIV, BUFGCTRL, and MBUFGCTRL buffers, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003). For details on connectivity and use of the BUFG_GT and MBUFG_GT buffers, see the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).