During analysis of critical paths, you can find multiple paths ending at control pins. Analyze these paths to determine if you can push logic into the datapath. Ensure this is done without incurring penalties. Avoid penalties like extra logic levels.
There is less delay in a path to the D pin than CE/R/S pins, given the same levels of logic. This is because there is a direct connection from the output of the last LUT to the D input of the FF. The following coding examples show how to push the logic from the control pin to the data pin of a register.
In the following example, the enable pin of dout_reg[0] has two logic levels, and the data pin has zero logic levels. In this situation, you can improve timing by moving the enable logic to the D pin. Set the EXTRACT_ENABLE attribute to "no" on the dout register definition in the RTL file.
The following example shows how to separate the combinational and sequential logic and map the complete logic in to the datapath. This pushes the logic into the D pin, which still has two logic levels.
You can achieve the same structure by setting the EXTRACT_ENABLE attribute to “no.” For more information on the EXTRACT_ENABLE attribute, refer to this link in the Vivado Design Suite User Guide: Synthesis (UG901).