The CLOCK_LOW_FANOUT constraint is used to contain the loads of a clock buffer to a single clock region. You can set the CLOCK_LOW_FANOUT constraint on a clock net segment directly driven by a global clock buffer or on a list of flip-flops.
Constraint Example for Clock Nets Driven by an XPIO Global Clock Buffer
If you set the CLOCK_LOW_FANOUT property on a clock net segment directly driven by a global clock buffer in an XPIO bank and the fanout of the global clock buffer is less than 4000 loads, the placement of the loads is contained to the clock region(s) that contain the BLI sites that have connectivity to the XPIO bank of the global clock buffer. This can be one or two clock regions vertically adjacent to the XPIO bank.
The following example shows the CLOCK_LOW_FANOUT constraint applied to the
clock net segment driven by a global clock buffer placed in XPIO bank 704. The input
clock port, CLK_P/CLK_N has a PACKAGE_PIN
assignment to a GCIO located in the XPIO bank 704 (clock region X4Y0) and drives an
XPLL. The XPLL drives a global clock buffer that subsequently drives the clock
network consisting of 1359 loads, including both BLI and non-BLI registers. The
loads of the global clock buffer are all placed in the clock regions directly above
XPIO bank 704 (clock regions X3Y1 and X4Y1) as seen in the following figure.
# PACKAGE_PIN BM26/BN27 - High Performance XPIO
set_property PACKAGE_PIN BN27
set_property IOSTANDARD LVDS15 [get_ports CLK_N]
set_property PACKAGE_PIN BM26
set_property IOSTANDARD LVDS15 [get_ports CLK_P]
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins BUFG_clkout1_inst/O]]Constraint Example for Clock Nets Driven by an HDIO Global Clock Buffer
If you set the CLOCK_LOW_FANOUT property on a clock net segment directly driven by a global clock buffer in an HDIO CLOCK_REGION and the fanout of the global clock buffer is less than 4000 loads, the placement of the loads is contained to the same CLOCK_REGION as the global clock buffer.
The following example shows the CLOCK_LOW_FANOUT constraint applied
to the clock net segment directly driven by a global clock buffer placed in the
HDIO. The input clock port, clkIn has a PACKAGE_PIN
assignment to a GCIO located in the HDIO CLOCK_REGION X0Y4 and drives a DPLL. The
DPLL drives a global clock buffer that subsequently drives the clock network with
128 loads. The loads of the global clock buffer are all placed in the CLOCK_REGION
X0Y4.
# PACKAGE_PIN L35 - High Density HDIO IOBank 306 - CLOCK_REGION X0Y4
set_property PACKAGE_PIN L35 [get_ports clkIn]
set_property IOSTANDARD LVCMOS33 [get_ports clkIn]
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins BUFG_clkout1_inst/O]]Constraint Example for Flip-Flops
Setting the CLOCK_LOW_FANOUT constraint on a list of flip-flops
driven by a global clock buffer causes opt_design
to create a new parallel global clock buffer to isolate the flip-flops. During
place_design, the isolated flip-flops that are
driven by the newly created parallel global clock buffer are contained to a single
clock region.
set_property CLOCK_LOW_FANOUT TRUE [get_cells safeClockStartup_reg[*]]In the design, an always-on clock network initially drives more than
4000 loads, including the flip-flops that are part of the clock gating
synchronization circuit used to clock gate other logic. The following schematics
show the clock gating synchronization circuit and additional logic connected to the
always-on clock network before and after opt_design
creates a new parallel global clock buffer to isolate the clock gating
synchronization circuit.
The Device window of the fully implemented design shows the clock gating synchronization circuit with green markers along with the always-on logic and clock-gated logic. The clock gating synchronization circuit is placed in a CLOCK_REGION that results in the minimal insertion delay from the BUFG in the XPIO.