Project-Based Simulation Flow Using VCS - 1.0 English

1. Open a QDR-IV SRAM example Vivado project (Open IP Example Design...), then under Add sources option, select the Add or create simulation sources option, and click Next.
2. Add the memory model in the Add or create simulation sources page and click Finish as shown.

   

3. In the Open IP Example Design Vivado project, under Flow Navigator, select Simulation Settings.
4. Select Target simulator as Verilog Compiler Simulator (VCS).
   1. Browse to the compiled libraries location and set the path on Compiled libraries location option.
   2. Under the Simulation tab, set the vcs.simulate.runtime to 1 ms (there are simulation RTL directives which stop the simulation after certain period of time, which is less than 1 ms) as shown in the following figure. The Generate Scripts Only option generates simulation scripts only. To run behavioral simulation, Generate Scripts Only option must be de-selected.
5. Apply the settings and select OK.
6. In the Flow Navigator window, select Run Simulation and select Run Behavioral Simulation option as shown:

   

7. Vivado invokes VCS and simulations are run in the VCS tool. For more information, see the Vivado Design Suite User Guide: Logic Simulation (UG900).