Port Descriptions - 1.0 English - PG355

There are three port categories at the top-level of the memory interface core called the “user design.”

• The first category is the memory interface signals that directly interfaces with the memory part. These are defined by the QDR-IV SRAM specification.
• The second category is the application interface signals which are referred to as the "user interface." These are described in the Protocol Description section.
• The third category includes other signals necessary for proper operation of the core. These include the clocks, reset, and status signals from the core. The clocking and reset signals are described in their respective sections.

  The active-High c0_init_calib_complete signal indicates that initialization and calibration are complete and that the interface is now ready to accept commands for the interface.

  Ensure that the commands are issued only after c0_init_calib_complete is High. Any commands issued before c0_init_calib_complete signal is High will be lost.