The user interface protocol for the QDR-IV SRAM is shown in the following figure.
Wait until the init_calib_complete
signal is asserted High before sending any command as shown in the previous figure. No read or
write requests are processed (that is, app_wr_cmd or app_rd_cmd on the client interface is ignored before init_calib_complete is High).
The previous figure shows various commands being issued for different channels from you. For channel 0 and 2, it is the write command and for 1 and 3 it is the read command. For details, see the Command Table section.
For the write commands, write address and write data has to be valid in the same
clock cycle as the write command. This means that for channel 0,
app_wrdata_a_ch0 is written at location app_addr_a_ch0. Also,
it is similar for channel 1.
For the read commands, read address has to be present at the time of
read commands assertion. The read data is available after a few clock cycles along with read
valid signal. In the previous figure, for channel 1, app_rddata_a_ch1 becomes available with the app_rddara_valid[1] signal.