The Versal ACAP PHY is composed of dedicated blocks and soft calibration logic. The dedicated blocks are structured adjacent to one another with back-to-back interconnects to minimize the clock and datapath routing necessary to build high performance physical layers.
The user interface/controller and calibration logic communicate with this dedicated PHY in the slow frequency clock domain, which is divided by 4. A more detailed block diagram of the PHY design is shown in the following figure.
| Module Name | Description |
|---|---|
| QDR-IV PHY | PHY top of QDR-IV design |
| QDR-IV Calibration | Calibration top module |
| QDR-IV Calibration Address Decoder | Versal ACAP logic interface for the MicroBlaze™ processor |
| QDR-IV Configuration ROM | Configuration storage for calibration options |
| MicroBlaze MCS | MicroBlaze processor |
| QDR-IV XPHY | Contains the XPHY instance |
| QDR-IV IOB Byte | Instantiates all byte IOB modules |
| QDR-IV IOB | QDR-IV |
The PHY architecture encompasses all of the logic contained in QDR-IV XPHY module. The PHY contains wrappers around dedicated hard blocks to build up the memory interface from smaller components. A byte lane contains all of the clocks, resets, and datapaths for a given subset of I/O. Multiple byte lanes are grouped together, along with dedicated clocking resources, to make up a single bank memory interface. For more information on the hard silicon physical layer architecture, see the Versal ACAP SelectIO Resources Architecture Manual (AM010).
The memory initialization and calibration are implemented in C programming on a small soft core processor. The MicroBlaze Controller System (MCS) is configured with an I/O Module, MicroBlaze Debug Module (MDM), and block RAM. The module QDR-IV Calibration Address Decoder provides the interface for the processor to the rest of the system and implements helper logic. The QDR-IV Configuration ROM module stores settings that control the operation of initialization and calibration, providing run time options that can be adjusted without having to recompile the source code.
The address unit connects the MCS to the local register set and the PHY by performing address decode and control translation on the I/O module bus from spaces in the memory map and MUXing return data (QDR-IV Calibration Address Decoder). In addition, it provides address translation (also known as “mapping”) from a logical conceptualization of the SRAM interface to the appropriate pinout-dependent location of the delay control in the PHY address space.
Although the calibration architecture presents a simple and organized address map for manipulating the delay elements for individual data, control and command bits, there is flexibility in how those I/O pins are placed. For a given I/O placement, the path to the Versal ACAP logic is locked to a given pin.