Pin and Bank Rules - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)
Document ID
PG355
Release Date
2021-12-03
Version
1.0 English
This section describes the pinout rules for QDR-IV SRAM (XP and HP) interface.
Important: The Versal soft memory IP can only use XPIO pins that are fully fabric accessible. Refer to the package file to determine XPIO pins that are fully fabric accessible. The XPIO pins/banks in a Versal device that are not fabric accessible are called shadow pins/banks.
  1. Each bank has nine nibbles numbered 0 to 8. Two consecutive nibbles in a bank are paired to form a nibble pair. For example, 0-1, 2-3, 4-5, and 6-7 are the four nibble pairs in a bank.
  2. Pins in a nibble are numbered 0 to 5. For example in the package pin name IO_L0N_XCC_N0P1_M0P1_700, N0P1 indicates pin 1 of nibble 0 in bank 700.
  3. Data Group: DQ pins, associated QK/QK# pins, and associated DK/DK# pins:
    1. Association of DQ, QK/QK#, and DK/DK#, pins are as per the QDR-IV data sheet (defined by Cypress® Semiconductor).
    2. For x18 component, PORT A signals, DQA[8:0], QKA[0]/QKA#[0], and DKA[0]/DKA#[0] are associated with a Data group; DQA[17:9], QKA[1]/QKA#[1]. DKA[1]/DKA#[1] are associated with another Data group. Similar data group association is followed for PORT B.
    3. For x36 component, PORT B signals, DQB[17:0], QKB[0]/QKB#[0], and DKB[0]/DKB#[0] are associated with a Data group; DQB[35:18], QKB[1]/QKB#[1]. DKB[1]/DKB#[1] are associated with another Data group. Similar data group association is followed for PORT A.
  4. Address/Control Group:
    1. Address group is defined as A, CK/CK#, AP, AINV pins of a single component.
    2. Control group is defined as PE#, LDA#, LDB#, RWA#, RWB#, CFG#, RST#, LBK0#, LBK1# pins of a single component.
  5. All the Address/Control group and Data group pins of a given memory interface design must be allocated within two consecutive banks for x18 component interfaces.
  6. All the Address/Control group and Data group pins of a given memory interface design must be allocated within three consecutive banks for x36 component interfaces.
  7. An interface is not limited within a given triplet. It can span across two triplets.
  8. Data Group (x18 Component):
    1. All the data groups of a single PORT must be allocated in a single bank.
    2. Data Group of PORT A can be swapped with Data Group of PORT B.
    3. Swapping of Data Nibbles within Data Group is allowed:
      • When data nibbles are swapped, QK/QK# and DK/DK# also must be moved along with DQ.
      • Swap of DQ pins with byte is allowed.
    4. DQ pins allocation:
      • All the DQ pins of a single data group can be allocated to any I/O pin in the Data Nibbles.
    5. QK/QK# pin allocation:
      • All the QK/QK# pair of a single data group must be allocated to pin-0/pin-1 P/N pair of any data nibble.
    6. DK/DK# pin allocation:
      • All the DK/DK# pair of a single data group can be allocated to any P/N pair in data nibble.
    7. Data groups of PORT A and PORT B of a single component cannot share nibbles.
    8. Single Data Nibble movement is not allowed.
    9. See the QDR-IV Pinout Examples section.
  9. Data Group (x36 Component):
    1. All the data groups of a single PORT must be allocated in a single bank.
    2. Data Group of PORT A can be swapped with Data Group of PORT B.
    3. Swapping of Data Nibbles within Data Group is allowed:
      • When data nibbles are swapped, QK/QK# and DK/DK# also must be moved along with DQ.
      • Swap of DQ pins with byte is allowed.
    4. Data Nibble cannot be in the eighth Nibble of Data Bank.
    5. DQ pins allocation:
      • All the DQ pins of a single data group can be allocated to any I/O pin in the Data Nibbles.
    6. QK/QK# pin allocation:
      • All the QK/QK# pairs of a single data group must be allocated to any pin-0/pin-1 P/N pair of any data nibble.
    7. DK/DK# pin allocation:
      • All the DK/DK# pairs of a single data group can be allocated to any P/N pair in data nibble.
    8. Data groups of PORT A and PORT B of a single component cannot share nibbles.
    9. Single Data Nibble movement is not allowed.
    10. See the QDR-IV Pinout Examples section.
  10. Address/Control pin allocation (x18 Component):
    1. All Address and Control group pins (as mentioned in 4.a and 4.b) must be allocated anywhere within two consecutive banks of the Interface.
    2. CK/CK# pin location is fixed as given in the default pin placement:
      • CK/CK# pair can be allocated to I/O PN pair only.
    3. Swapping of Address pins is allowed within an Address Group.
    4. Control pins can be anywhere in the two banks. Address and Control pins can be in different bank.
    5. Swapping between Address and Control pins is not allowed.
    6. Pins A, AP, PE#, AINV, LDA#, LDB#, RWA#, RWB#, CFG#, RST#, LBK0#, and LBK1# of the design can be allocated to any I/O pin.
  11. Address/Control pin allocation (x36 Component):
    1. All Address and Control group pins must be placed in middle bank only.
    2. Swapping of Address pins is allowed within an Address Group.
    3. Control pins can be anywhere in the middle bank.
    4. Swapping between Address and Control pins is not allowed.
    5. CK/CK# pin location is fixed as given in the default pin placement.
      • CK/CK# pair can be allocated to I/O PN pair only.
  12. System clock pin must be allocated within the Interface banks (In the case of x18, the sys_clk_p/n must be allocated to any differential pin pair within the two interface banks. In the case of x36, the sys_clk_p/n pins must be allocated to any differential pin pair within the three interface banks).
  13. System Control/Status signals (init_calib_complete, data_compare_error, sys_rst_n) can be allocated to any fabric accessible bank in the device including memory interface banks.
  14. The IO_VP pin is an additional bank pin that is used as a reference to calibrate internal on-die termination (DCI). This pin must be externally connected to a 240Ω resistor on the PCB and pulled up to the bank VCCO voltage. DCI is required for this interface. All rules for the DCI in the Versal ACAP SelectIO Resources Architecture Manual (AM010) must be followed.
    Recommended: Xilinx strongly recommends that the DCIUpdateMode option is kept with the default value of ASREQUIRED so that the DCI circuitry is allowed to operate normally.
  15. Versal ACAP XPIO only supports internally generated VREF. See the Versal ACAP SelectIO Resources Architecture Manual (AM010) for details.
  16. The system reset pin (sys_rst_n) can be placed on any spare pin within the two or three banks of the interface.
    Important: QDR-IV IP does not support data inversion. Contact your memory vendor for terminating DINVA and DINVB at memory.
    Important: QDR-IV IP does not support output data valid indicator. Contact your memory vendor for terminating QVLDA and QVLDB at memory.
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