Channel Wise Command Order to the Memory - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)

Document ID
PG355
Release Date
2021-12-03
Version
1.0 English

The following figure shows the channel wise command order when there is no command switch from read to write (vice-versa) and no collision. Channel 0 PORT A is sent to the memory interface first, followed by channel 0 PORT B, followed by channel 1 PORT A, followed by channel 1 PORT B, etc.

Figure 1. Command Order to the Memory