Calibration Status Register Signal Description - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)
Document ID
PG355
Release Date
2021-12-03
Version
1.0 English
Table 1. Calibration Status Register Signal Description
Status Register Bits Description
cal_status[31:0] 0 PHY ready asserted
1 QDR-IV Initialization completed
2 Address Control Calibration completed
3 DK to CK Alignment completed
4 Simple Read Calibration completed
5 Simple Write Calibration completed
6 Write Data Bitslip Correction completed
7 Read Data Bitslip Correction completed
8 Read Valid Calculation Completed
9 Complex Address Centering completed
10 Complex Read Centering completed
11 Complex Write Centering completed
15:12 Reserved
16 PHY ready failed to assert
17 QDR-IV Initialization failed to complete
18 Address Control Calibration failed to complete
19 DK to CK Alignment failed to complete
20 Simple Read Calibration failed to complete
21 Simple Write Calibration failed to complete
22 Write Data Bitslip Correction failed to complete
23 Read Data Bitslip Correction failed to complete
24 Read Valid Calculation failed to complete
25 Complex Address Centering failed to complete
26 Complex Read Centering failed to complete
27 Complex Write Centering failed to complete
31:28 Reserved