There are two types of debug signals used in Memory IP Versal ACAP debug. The first set is part of a debug
interface that is always included in generated Memory IP Versal ACAP designs. This includes the init_calib_complete signal.
The second type of debug signals are fully integrated in the IP when the Debug Signals option in the Memory IP tool is enabled and when using the Memory IP Example Design. These signals are connected to the debug ILA and VIO core.