To focus the debug on calibration or data errors, use the provided Memory IP example design on the targeted board with the Debug Feature enabled through the Memory IP Versal® adaptive compute acceleration platform (ACAP) GUI.
However, the debug signals and example design are required to analyze the provided Integrated Logic Analyzer (ILA) and VIO debug signals within the Vivado Design Suite debug feature. The latest Memory IP release should be used to generate the example design.