The physical interface is the connection from the Versal ACAP memory interface solution to an external QDR-IV SRAM device. The I/O signals for this interface are defined in the following table. These signals can be directly connected to the corresponding signals on the memory device.
| Signal | I/O | Description |
|---|---|---|
| ck | I | Address/Command Input Clock. CK is differential clock input. All control and address input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples the control and address inputs for PORT A, while the falling edge of CK samples the control and address inputs for PORT B. |
| ck_n | I | CK# is 180° out of phase with CK. |
| A[x:0] | I | Address Inputs. Sampled on the rising edge of both CK and CK# clocks during
active read and write operations. These address inputs are used for read and write
operations on both ports. For (×36) data width, Address inputs A[20:0] are used and A[24:21] are reserved. For (×18) data width, Address inputs A[21:0] are used and A[24:22] are reserved. The reserved address inputs are No Connects and might be tied High, Low, or left floating. |
| AP | I | Address Parity Input. Used to provide even parity across the address pins. For (×36) data width, AP covers address inputs A[20:0]. For (×18) data width, AP covers address inputs A[21:0]. |
| PE_n | O | Address Parity Error Flag. Asserted Low when address parity error is detected. After asserted, PE# remains Low until cleared by a Configuration register command. |
| AINV | I |
Address Inversion Pin for Address and Address Parity Inputs. For (x36) data width, AINV covers address inputs A[20:0] and the address parity input (AP). For (x18) data width, AINV covers address inputs A[21:0] and the address parity input (AP). |
| DKA[1:0], DKA_n[1:0] |
I | DKA[0]/DKA#[0] controls the DQA[17:0] inputs for x36 configuration and DQA[8:0]
inputs for x18 configuration, respectively. DKA[1]/DKA#[1] controls the DQA[35:18] inputs for x36 configuration and DQA[17:9] inputs for x18 configuration, respectively. |
| DKB[1:0], DKB_n[1:0] |
I | DKB[0]/DKB#[0] controls the DQB[17:0] inputs for x36 configuration and DQB[8:0]
inputs for x18 configuration, respectively. DKB[1]/DKB#[1] controls the DQB[35:18] inputs for x36 configuration and DQB[17:9] inputs for x18 configuration, respectively. |
| QKA[1:0], QKA_n[1:0] |
O | Data Output Clock. QKA[0]/QKA#[0] controls the DQA[17:0] outputs for x36 configuration and DQA[8:0] outputs for x18 configuration, respectively. QKA[1]/QKA#[1] controls the DQA[35:18] outputs for x36 configuration and DQA[17:9] outputs for x18 configuration, respectively. |
| QKB[1:0], QKB_n[1:0] |
O | QKB[0]/QKB#[0] controls the DQB[17:0] outputs for x36 configuration and
DQB[8:0] outputs for x18 configuration, respectively. QKB[1]/QKB#[1] controls the DQB[35:18] outputs for x36 configuration and DQB[17:9] outputs for x18 configuration, respectively. |
| LDA_n | I | Synchronous Load Input. LDA_n is sampled on the rising edge of the CK clock. LDA_n enables commands for data PORT A. LDA_n enables the commands when LDA_n is Low and disables the commands when LDA_n is High. When the command is disabled, new commands are ignored, but internal operations continue. |
| LDB_n | I | Synchronous Load Input. LDB_n is sampled on the falling edge of the CK clock. LDB_n enables commands for data PORT B. LDB_n enables the commands when LDB_n is Low and disables the commands when LDB_n is High. When the command is disabled, new commands are ignored, but internal operations continue. |
| RWA_n | I | Synchronous Read/Write Input. RWA_n input is sampled on the rising edge of the CK clock. The RWA_n input is used with the LDA_n input to select a read or write operation. |
| RWB_n | I | RWB_n input is sampled on the falling edge of the CK clock. The RWB_n input is used with the LDB_n input to select a read or write operation. The RWB_n input is used with the LDB_n input to select a Read or Write operation. |
| CFG_n | I | Configuration bit. This pin is used to configure different mode registers. |
| RST_n | I | Active-Low Asynchronous RST. This pin is active when RST# is Low and inactive when RST# is High. The RST# pin has an internal pull-down resistor. |
| LBK0_n, LBK1_n |
I | Loopback mode for control and address/command/clock deskewing. |
The following figure shows the timing diagram for the sample write and read operations at the memory interface with write latency of three clock cycles and read latency of five clock cycles, respectively.
The command is detected by the memory only when LDA_n and LDB_n are Low for PORT A and PORT B, respectively. When RWA_n is Low, it is write command and when it is High, it is a read command. This is true for PORT B as well. Address is DDR and hence on the rising edge of CK, address is considered to be valid for PORT A and on the falling edge it is considered for PORT B.
In the figure, the cursor position is pointing to PORT A write
command. Write address is 0x050EE8. The DDR data is written into the memory
as 0xC_6B7* and 0x0_57B* with the write latency at three
clock cycles.
Following falling edge is a PORT B write command at address
0x0A7BC4 and the DDR data which is written to this memory address at PORT
B is 0xF_754* and 0x7_7B2.
Next, the CK rising edge is a PORT A read command at address
0x0E6741 and corresponding data becomes available at the
DQA data bus after five CK clock cycles aligned to the rising edge of QK clock edge because
the read latency is five. The DDR read data is 0xC_818*
and 0xA_150*.
