Note: Only enabled for data rates above 1,600 Mb/s.
The purpose of using a complex pattern is to stress the system for SI effects such as ISI and noise while calculating the write clock DK center and write DQ positions. This ensures the write center position can reliably capture data with margin in a true system.
Complex Write Calibration is accomplished as follows:
- Complex patterns are written to the QDR-IV and read back.
- Increment ODELAY of DQ bits until error is detected in the read data. This is the new left edge of the write data window and left margin is calculated as: Current ODELAY – Initial ODELAY
- Revert the ODELAY of DQ bits to the value found during Simple Write Calibration stage. Decrement ODELAY of DQ bits until error is detected in the read data. This is the new right edge of the write data window and right margin is calculated as: Initial ODELAY – Current ODELAY
- Update the center tap location of DQ bits based on left margin and right
margin.
- Final ODELAY = Initial ODELAY + (Left Margin – Right Margin)/2