Bank Collision - 1.0 English - PG355

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)
Document ID
PG355
Release Date
2021-12-03
Version
1.0 English
Note: HP memory devices do not have bank access restriction so bank collision does not apply when you are dealing with HP memory devices.

The last three bits of the address denote which bank out of the eight available banks in the memory device is being accessed. The rule as per the memory access for XP part is that PORT B cannot access the same bank in the same clock cycle as PORT A. Because there are four channels, the bank comparison for collision is done on a per-channel basis. If a collision is found on any of the four channels, all of the four channels of the corresponding ports are affected as explained in the later sections.

For detecting whether there is a collision, the last three bits of the channel address are compared. The following conditions are checked for collision detection:

  1. Comparison is done channel-wise. That is, PORT A channel 0 is compared with PORT B channel 0. PORT A channel 0 is never compared with PORT B channel 1 or any other channel.
  2. Only the last three bits of the channel address is compared. They all should match for collision to be detected.
  3. Restriction for accessing the same bank in the same cycle only lies with PORT B and not on PORT A. This means that for detecting the collision, the last three bits of channel 0 PORT A is compared with the last three bits of channel 0 of PORT B.

PORT B channel 0 is not compared with PORT A channel 1 for collision detection. This is illustrated in the following figure.

Figure 1. Bank Address Comparison for Collision

Because of the four channels per port sending commands in every clock, there is an order in which the command is called by the controller towards the memory.

The following figure shows how the bank collision signals for PORT A and PORT B are asserted. To begin, the priority remains with PORT A for accessing any bank. If PORT B tries to access (read command or write command) the same bank in the same clock, it is considered a PORT B collision. Therefore, Bank_collision_B signal is asserted and the controller delays the processing of PORT B command by one user clock.

If PORT A accesses the same bank again after the pending PORT B command is serviced, it is considered a PORT A collision. PORT A command processing is delayed by one user clock. This is done to provide equal opportunity to both the ports in case they are trying to access the same bank back-to-back.

The following figure takes channel 0 as an example and is true for all the channels.

Figure 2. Bank Collision Signals for PORT A and PORT B

From the previous figure, there is a bank collision on PORT A or B and a corresponding ready is deasserted. It is your responsibility to ensure that it should not issue any command after it samples a ready to be Low (that is, hold its next command transaction until ready is asserted back). The command issued while ready is Low is lost for all four channels corresponding to the port as app_cmd_rdy_a and app_cmd_rdy_b are common for all four channels.

Note: Because there are four channels per port, collision on one channel delays the command processing for all four channels for that port. The following simulation snapshot explains this scenario.
Figure 3. Bank Collision Simulation

For example, the first collision occurs on PORT B channel 0 because PORT B wants to access the same bank in the same user clock. Then, the controller stores PORT B commands for all four channels and deasserts the PORT B ready signal. It is your responsibility to hold the next set of commands for PORT B until the user interface asserts the ready signal. If you issue another set of commands when the ready is Low, those commands for all four channels are lost and it does not go to the memory interface.