The example design provides a synthesizable test bench to generate a fixed
simple data pattern to the Memory Controller. This test bench consists of an IP wrapper and an
example_tb that generates 16 writes and 16 reads. QDR-IV SRAM does not deliver the QDR-IV memory models. The memory model required for the simulation must be
downloaded from the memory vendor's website.
The example design can be simulated using one of the methods in the following sections.