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Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017)

Document ID
AM017
Release Date
2024-09-05
Revision
1.1 English

The following figure shows the write transfer timing diagram.

Figure 1. Write Transfer

At T1, a write transfer starts with address APB3PADDR, write data APB3PWDATA, write signal APB3PWRITE, and select signal APB3PSEL, being registered at the rising edge of APB3CLK. This is called the Setup phase of the write transfer.

At T2, enable signal APB3PENABLE and ready signal APB3PREADY are registered at the rising edge of APB3CLK. When asserted, APB3PENABLE indicates the start of the Access phase of the transfer. When asserted, APB3PREADY indicates that the slave can complete the transfer at the next rising edge of APB3CLK.

The address APB3PADDR, write data APB3PWDATA, and control signals all remain valid until the transfer completes at T3, the end of the Access phase.

The enable signal APB3PENABLE is deasserted at the end of the transfer. The select signal APB3PSEL is also deasserted unless the transfer is to be followed immediately by another transfer to the same peripheral.

Figure 2. Read Transfer

The timing of the address, write, select, and enable signals are as described for write transfers. The slave must provide the data before the end of the read transfer.

APB3ADDR must not be set in the range of 0x00 through 0x0C even though the actual read or write transaction is not performed. If it happens, the data from the next subsequent read must be discarded.