The RX programmable divider shown in RX Fabric Clock Output Control uses the recovered clock from the CDR to generate a parallel
output clock. By using the recovered clock, RX programmable divider, and BUFG_GT,
CH*_RXOUTCLK (RXOUTCLKCTL = 3'b101) can be used as a clock
source for the interconnect logic instead of consuming PLL or MMCM resources in the
interconnect logic. The output clock of the programmable divider can also be brought out to
the transceiver reference clock pin configured as an output. The supported divider values
are 4, 5, 5.5, 8, 10, 16, 16.5, 20, 32, 33, 40, 64, and 66.