PLL Power Down

Versal ACAP GTM Transceivers Architecture Manual (AM017)

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To activate the LCPLL power-down mode, the active-High HSCLK*_LCPLLPD signal is asserted. When HSCLK*_LCPLLPD is asserted, the PLL is powered down. As a result, all clocks derived from the PLL are stopped. Recovery from this power state is indicated by the assertion of the PLL lock signal HSCLK*_LCPLLLOCK.