Quad Sharing with Multiple IP Cores

Versal ACAP GTM Transceivers Architecture Manual (AM017)

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When multiple IP cores are located within the same Quad, there are limitations on how the reset can be performed. When an IP core asserts the master reset, the corresponding PLL that it uses also goes through reset. If any other IP within the same Quad shares the same PLL, its operation will be affected. In this situation, any IP that shares the same PLL within the same Quad must perform reset at the same time.